Patents by Inventor Ren-Yi Cheng

Ren-Yi Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11956869
    Abstract: A display driver circuit for controlling a display panel having a plurality of light-emission diode (LED) strings includes a plurality of current regulators and a control circuit. Each of the plurality of current regulators is configured to control one of the plurality of LED strings. The control circuit, coupled to the plurality of current regulators, is configured to generate a plurality of pulses in a plurality of pulse width modulation (PWM) signals and output each of the plurality of PWM signals to a respective current regulator among the plurality of current regulators. Wherein, the plurality of pulses are scrambled.
    Type: Grant
    Filed: October 12, 2022
    Date of Patent: April 9, 2024
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Chih-Hsien Chou, Jhih-Siou Cheng, Jin-Yi Lin, Ren-Chieh Yang
  • Patent number: 8143101
    Abstract: The present invention relates to semiconductor package and the method of making the same. The method of the invention comprises the following steps: (a) providing a first substrate; (b) mounting a first chip onto a surface of the first substrate; (c) forming a plurality of conductive elements on the surface of the first substrate; (d) covering the conductive elements with a mold, the mold having a plurality of cavities accommodating top ends of each of the conductive elements; and (e) forming a first molding compound for encapsulating the surface of the first substrate, the first chip and parts of the conductive elements, wherein the height of the first molding compound is smaller than the height of each of the conductive elements. Thus, the first molding compound encapsulates the entire surface of the first substrate, so that the mold flush of the first molding compound will not occur, and the rigidity of the first substrate is increased.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: March 27, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Ching Sun, Ren-Yi Cheng, Tsai Wan, Chih-Hung Hsu, Kuang-Hsiung Chen
  • Patent number: 7927924
    Abstract: The present invention relates to a semi-finished package and a method for making a package. The semi-finished package includes a carrier and at least one molding compound. The molding compound is disposed on a surface of the carrier, and has a body and a plurality of outer protrusions. The outer protrusions are disposed at the periphery of the body, and the height of the outer protrusions is greater than that of the body. Thus, by utilizing the outer protrusions, the rigidity of the semi-finished package is increased, so as to overcome the warpage of the semi-finished package caused by different coefficients of thermal expansion of the molding compound and the carrier. Therefore, the yield rate of the package unit is increased.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: April 19, 2011
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Ren-Yi Cheng, Kuang-Hsiung Chen, Chun-Hung Hsu
  • Publication number: 20090278253
    Abstract: The present invention relates to a semi-finished package and a method for making a package. The semi-finished package includes a carrier and at least one molding compound. The molding compound is disposed on a surface of the carrier, and has a body and a plurality of outer protrusions. The outer protrusions are disposed at the periphery of the body, and the height of the outer protrusions is greater than that of the body. Thus, by utilizing the outer protrusions, the rigidity of the semi-finished package is increased, so as to overcome the warpage of the semi-finished package caused by different coefficients of thermal expansion of the molding compound and the carrier. Therefore, the yield rate of the package unit is increased.
    Type: Application
    Filed: April 30, 2009
    Publication date: November 12, 2009
    Inventors: Ren-Yi Cheng, Kuang-Hsiung Chen, Chun-Hung Hsu
  • Publication number: 20080230887
    Abstract: The present invention relates to semiconductor package and the method of making the same. The method of the invention comprises the following steps: (a) providing a first substrate; (b) mounting a first chip onto a surface of the first substrate; (c) forming a plurality of conductive elements on the surface of the first substrate; (d) covering the conductive elements with a mold, the mold having a plurality of cavities accommodating top ends of each of the conductive elements; and (e) forming a first molding compound for encapsulating the surface of the first substrate, the first chip and parts of the conductive elements, wherein the height of the first molding compound is smaller than the height of each of the conductive elements. Thus, the first molding compound encapsulates the entire surface of the first substrate, so that the mold flush of the first molding compound will not occur, and the rigidity of the first substrate is increased.
    Type: Application
    Filed: March 21, 2008
    Publication date: September 25, 2008
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Ching Sun, Ren-Yi Cheng, Tsai Wan, Chih-Hung Hsu, Kuang-Hsiung Chen