Abstract: Methods and systems for image processing are provided. A particular method includes receiving a video object plane (VOP) at an image processing device and decoding the received VOP. The method also includes storing an order number of the decoded VOP at a P-VOP queue in a memory of the image processing device when the received VOP is a predictive coded VOP (P-VOP). The method further includes storing the order number of the decoded VOP at a first available location of a display ordered read queue in the memory of the image processing device when the received VOP is not a P-VOP.

Abstract: Methods and systems for image processing are provided. A particular method includes receiving a video object plane (VOP) at an image processing device and decoding the received VOP. The method also includes storing an order number of the decoded VOP at a P-VOP queue in a memory of the image processing device when the received VOP is a predictive coded VOP (P-VOP). The method further includes storing the order number of the decoded VOP at a first available location of a display ordered read queue in the memory of the image processing device when the received VOP is not a P-VOP.

Abstract: A device and a method are disclosed for motion estimation and bandwidth reduction in a memory. The device includes a memory for storing a plurality of frame data, a controller connected to the memory, a first motion estimation processor for performing a coarse-tuning operation and a second motion estimation processor for performing a fine-tuning operation. Similarity between a reference frame and a current frame is calculated based on the averages of every two adjacent pixels in the reference macroblocks and current macroblocks. The amount of calculations for determining motion estimation is greatly reduced, and bandwidth in utilizing the memory is accordingly reduced as motion estimation is advantageously achieved.

Abstract: An implementation of an MPEG-4 compliant post-filter for image data, which performs deblocking and deringing post-filtering on decoded video data. The post-filter comprises two independent processing units, one for horizontal deblocking and the other for vertical deblocking and deringing, each processing unit in communication with a memory system, which can include DRAM. The post-filter further comprises a local memory, which can be SRAM, for high speed access to data being processed by the vertical deblocking and deringing filter, without additional accesses to the memory system. Further, horizontal deblocking and vertical deblocking and deringing functions can be performed concurrently in a pipe-lined fashion.

Abstract: The invention provides a system and method for memory bus assignment for a plurality of functional devices. According to a preferred embodiment, the invention provides a system comprising a plurality of functional devices accessing a memory bus wherein the memory bus allows access by one of the functional devices for one cycle of period of time, a plurality of request agents corresponding to the functional devices, a control register respectively storing access priority grades for the request agents, a plurality of counter timers respectively loading the access priority grades; and a bus elector coupled with the counter timers wherein the bus elector respectively compares the loaded access priority grades and elects one out of the request agents according to the compared access priority grades. The memory bus accordingly allows access by one of the functional devices corresponding to the elected request agent for one cycle of period of time.

Abstract: The invention generally relates to image processing and, more particularly, to display order of video object planes (VOPs) of images. The method according to a preferred embodiment of the invention primarily comprises the steps of arranging a first queue of a plurality of cells with a first order, providing a second queue of a single cell storing an order number, decoding the incoming video object planes (VOPs), determining whether the incoming VOPs are intra coded (I-VOPs), determining whether the incoming VOPs are predictive coded (P-VOPs), determining whether the incoming VOPs are bidirectional predictive coded (B-VOPs), and registering one of the plurality of cells of the first queue with a VOP incoming order for the incoming VOPs that are I-VOPs or B-VOPs.

Abstract: The invention advantageously provides a method for motion estimation and bandwidth reduction in a memory and a device for performing the same. The device according to the invention includes a memory for storing a plurality of frame data, a controller connected to the memory, a first motion estimation processor for performing a coarse-tuning operation and a second motion estimation processor for performing a fine-tuning operation. Similarity between a reference frame and a current frame is calculated based on the averages of every two adjacent pixels in the reference macroblocks and current macroblocks. The amount of calculations for determining motion estimation is greatly reduced, and bandwidth in utilizing the memory is accordingly reduced as motion estimation is advantageously achieved.

Abstract: The invention provides a system and method for memory bus assignment for a plurality of functional devices. According to a preferred embodiment, the invention provides a system comprising a plurality of functional devices accessing a memory bus wherein the memory bus allows access by one of the functional devices for one cycle of period of time, a plurality of request agents corresponding to the functional devices, a control register respectively storing access priority grades for the request agents, a plurality of counter timers respectively loading the access priority grades; and a bus elector coupled with the counter timers wherein the bus elector respectively compares the loaded access priority grades and elects one out of the request agents according to the compared access priority grades. The memory bus accordingly allows access by one of the functional devices corresponding to the elected request agent for one cycle of period of time.

Abstract: An implementation of an MPEG-4 compliant post-filter for image data, which performs deblocking and deringing post-filtering on decoded video data. The post-filter comprises two independent processing units, one for horizontal deblocking and the other for vertical deblocking and deringing, each processing unit in communication with a memory system, which can include DRAM. The post-filter further comprises a local memory, which can be SRAM, for high speed access to data being processed by the vertical deblocking and deringing filter, without additional accesses to the memory system. Further, horizontal deblocking and vertical deblocking and deringing functions can be performed concurrently in a pipe-lined fashion.

Abstract: An apparatus for edge enhancement of a digital image provided as raw digital image data to an input terminal and for providing processed image data to an output terminal. An offset processing circuit is coupled to the input terminal and configured to receive the raw data and generate offset data. An interpolation circuit is coupled to the offset processing circuit and configured to receive the offset data and to provide interpolated data. A color processing circuit is coupled to the interpolation circuit and configured to process the interpolated data to generate color data. An edge enhancement circuit is coupled to the interpolation circuit and the color processing circuit and configured to enhance the edges of the image based on the interpolated data and the color data to generate enhanced data. A lookup table is coupled to the color processing circuit and the edge enhancement circuit and configured to lookup the color data and the enhanced data to generate lookup data.

Abstract: “An image processing system, in which bit shuffling is done in order to maintain image quality, stores digitized video data bits stream in a conventional memory, such as a DRAM. The image processing system is suitable for widely-used image compression standards that integrate various algorithms into a compression system, such as the standards specified in the Digital Video Standard (the DV-SD standard, or “Blue Book”). The image processing system receives a number of blocks associated with a first video frame and stores these blocks in the DRAM. The image processing system receives and stores blocks associated with a second video frame in the DRAM. The image processing system, processes the blocks of the first video frame while storing the blocks of the second video fame.

Abstract: A method and apparatus for concatenating data words from a bitstream includes a scratch memory (802, 902) containing last words of unfinished blocks and left-aligned extra data words of finished blocks. A previous register (808, 908) holds one last word of an unfinished block. A next register (806, 906) holds a first of possibly many extra data words associated with the last word. A bit detector (810, 910), coupled to the previous register (808, 908) and the next register (806, 906), first concatenates the last word and the first extra data word and identifies selected bits for the detection of a valid code word. When no more valid code words can be found from the selected bits, and more data associated with the unfinished block exists, the first extra data word is moved to the previous register (808, 908) and a second extra data word is moved to the next register (806, 906). The first extra data word and the second extra data word are concatenated for the detection of another valid code word.

Abstract: New and improved methods and apparatus for run-length encoding video data. These techniques are especially suited to digital video applications, in which input to a video decoder is generated in order to determine run lengths and amplitudes. The implementations are suitable for widely-used image compression standards that integrate various algorithms into a compression system, such as the standards specified in the Digital Video Standard (the “Blue Book”).

Abstract: New and improved methods and apparatus for code packing in a digital video system. Among others, a method of transferring a data block to a storage device is disclosed. The storage device can include a plurality of compartments. The method includes receiving a plurality of length values. Each length value can correspond to a data block from a plurality of data blocks. The method further includes filling a first compartment of the storage device with a portion of data from a first data block, searching the length values to identify one of the plurality of data blocks having a length value less than a threshold value, and filling a second compartment with a remaining portion of the data from the first data block. In one embodiment, the second compartment can correspond to the identified data block.

Abstract: New and improved apparatus and methods for video encoding, for example, to efficiently and concurrently apply adaptive encoding techniques to convert analog data into digital formats, such as Digital Video (DV) format. A parallel system receives a block of video data and based on the computations and comparisons performed determines the best quantization factor for the block of video data. In an embodiment, the parallel system performs selected operations in parallel to save time and increase speed.

Abstract: New and improved methods and apparatus for concatenating data words from a bitstream. These techniques are especially suited to digital video applications, in which input to a video decoder is generated in order to determine run lengths and amplitudes. This implementation is suitable for widely-used image compression standards that integrate various algorithms into a compression system, such as the standards specified in the Digital Video Standard (the “Blue Book”).

Abstract: A method and apparatus for providing audio in a digital video system. Equations for a value n are provided for replacement into the conventional audio data shuffling equations. The equations for the value n provide for simple, efficient techniques to, in turn, calculate values for track number (TK), block number (BK), and data position number (DP). The values TK, BK, DP can be used in an address generation scheme to generate a page value and an offset value. The page value and the offset value for a particular sample of digital audio data, in part, determine the location of the sample in a memory storing the digital audio data. The present invention can be implemented for both four channel and two channel modes under both the NTSC and the PAL standards in accordance with specifications set forth in the Digital Video Standard (the “Blue Book”).

Abstract: New and improved apparatus and methods for video encoding, for example, to efficiently and concurrently encode video data into digital formats, such as Digital Video (DV) format. A pipelined system receives a block of video data and based on the computations and comparisons concurrently performed on the pixels within the block of video data determines which type of transformation is most appropriate for a given block of video data.

Abstract: An image compression apparatus for compressing image data provided to an input terminal and providing compressed data to an output terminal includes a 4×4 weighted digital cosine transformer (DCT) coupled to the input terminal and configured to convert the image data into weighted frequency data. A zigzag circuit is coupled to the DCT and configured to zigzag process the frequency data and generate create zigzag data. A Q-factor estimator is coupled to the DCT and configured to estimate the frequency data and generate a Q-factor. A DC coding circuit is coupled to the zigzag circuit and configured to code the zigzag data and generate a DC code. A quantization circuit is coupled to the zigzag circuit and the Q-factor estimator and configured to quantize the zigzag data based on the Q-factor and generate quantized data.

Abstract: An apparatus and method for determining inter-frame motion during compression of digital video data incorporates a computationally efficient hierarchical block-matching motion estimation technique in conjunction with a full-search block-matching approach. In the hierarchical block-matching method, a macroblock is filtered and decimated, and a search area is also filtered and decimated. A block-matching search is performed within the filtered and decimated search area. An augmented block in the original search area that corresponds to the block in the decimated search area that provided the best match with the decimated macroblock is then compared with the original macroblock to determine a motion vector. Operating parameters specify the search range based on the type of frame being processed, i.e. P-frame or B-frame, and, in the case of B-frames, the distance of the B-frame from the reference frame.