Abstract: An accelerated electron detector comprises an array of monolithic sensors in a CMOS structure, each sensor comprising a substrate (10), an epi layer (11), a p+ well (12) and n+ wells (13) which are separated from the p+ well (12) by the epi layer (11). Integrated in the p+ well are a plurality of NMOS transistors. The sensor also includes a deep n region (15) beneath the p+ well (12) which establishes within the epi layer a depletion layer so that on application of a biasing voltage charge carriers generated in the epi layer are caused to drift to the n+ well (13). The detector has improved radiation hardness and it therefore suitable for the detection and imaging of accelerated electrons such as in electron microscopes.

Abstract: An imaging device comprising a two-dimensional array of pixels which are scanned to build up a desired image. Each pixel comprises a sensor such as a photodiode PD which outputs a signal dependent upon the strength of the incident radiation. This signal is amplified in an inverter circuit MB1, MIN and switched by transistors MW1, MW2 which in turn are controlled by a write signal applied to their connected gate electrodes. During the write period, the output signal from photodiode PD is passed to a line (4) which is input to a number n+1 of memory cells MO to Mn which are switched sequentially via respective control inputs sample to sample to receive and store respective samples of the amplified signal from photodiode PD. The stored samples are read out sequentially over a read period during which a read transistor MSE, controlled by a read signal at its gate electrode, connects the memory cells to an output terminal (3) connected to the column bus.