Patents by Inventor Rene Gallezot
Rene Gallezot has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8995445Abstract: In a network device packets are marked with sequence identifiers at ingress of the device, switched through a plurality of switching planes and re-sequenced on a per flow basis at egress of the device. The re-sequencing system includes a controller that allocates to each received data packet a temporary storage location in a packet buffer. A plurality of output registers are provided, with each one associated with a flow. A pointer uses predefined parameters to point to an output register that has been previously assigned to receive data packets from the corresponding flow. Parameters in the pointed output register are correlated with parameters in a received packet to determine if the received packet is next in sequence to packets processed through a particular queue.Type: GrantFiled: November 26, 2003Date of Patent: March 31, 2015Assignee: International Business Machines CorporationInventors: Francois Le Maut, Rene Glaise, Michel Poret, Rene Gallezot
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Patent number: 8055984Abstract: A method for combining a simple forward error correction code i.e., a Hamming-like code with scrambling and descrambling functions is disclosed. Therefore, irrespective of the information to be transported, received data may be corrected, bit error spreading effects being handled, while providing desirable signal characteristics such as signal DC balance and enough signal transitions. The overhead introduced by the method is a modest increase over the original overhead of the 10 Gb Ethernet 64B/66B code.Type: GrantFiled: July 11, 2007Date of Patent: November 8, 2011Assignee: International Business Machines CorporationInventors: Rene Gallezot, Rene Glaise, Michel Poret
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Patent number: 7839797Abstract: A method for controlling the flows of data packets that are switched or routed at nodes of high-speed communication networks is disclosed. According to the invention, resource metering units are assigned to resources shared between devices of the switch or router e.g., shared memories or link bandwidths. When the occupancy of a shared resource reaches a predetermined threshold, an event is generated and transmitted to devices sharing this resource. Furthermore, a periodic refresh of the overall flow control information is performed so that lost events are, however, eventually acted on. Thus, a new device may become active without perturbing the active flows after having gathered enough flow control information.Type: GrantFiled: September 17, 2007Date of Patent: November 23, 2010Assignee: International Business Machines CorporationInventors: Rene Gallezot, Rene Glaise, Francois Le Maut
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Patent number: 7787446Abstract: A system for controlling egress buffer saturation includes, for each data packet flow, a comparator for comparing the number of data packets ‘WPC’ temporarily stored within an egress buffer to a predefined threshold value ‘WPCth’. The packet sequence number ‘PSNr’ of a last received in-sequence data packet and each highest packet sequence number ‘HPSNj’ received through respective ones of the plurality of switching planes is stored. By comparing the last received in-sequence packet sequence number ‘PSNr’ to each highest packet sequence number ‘HPSNj’ when the number of data packets ‘WPC’ exceeds the predefined threshold value ‘WPCth’ a determination as to which switching plane(s), among the plurality of switching planes, to unstop the flow of data packets can be made.Type: GrantFiled: May 23, 2008Date of Patent: August 31, 2010Assignee: International Business Machines CorporationInventors: Francois Le Maut, Rene Glaise, Michel Poret, Rene Gallezot
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Patent number: 7773602Abstract: An embodiment of the system operates in a parallel packet switch architecture having at least one egress adapter arranged to receive data packets issued from a plurality of ingress adapters and switched through a plurality of independent switching planes. Each received data packet belongs to one sequence of data packets among a plurality of sequences where the data packets are numbered with a packet sequence number (PSN) assigned according to at least a priority level of the data packet. Each data packet received by the at least one egress adapter has a source identifier to identify the ingress adapter from which it is issued. The system for restoring the sequences of the received data packets operates within the egress adapter and comprises buffer for temporarily storing each received data packet at an allocated packet buffer location, a controller, and a determination means coupled to a storing means and extracting means.Type: GrantFiled: May 20, 2008Date of Patent: August 10, 2010Assignee: International Business Machines CorporationInventors: Alain Blanc, Rene Glaise, Michel Poret, Rene Gallezot
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Publication number: 20080267206Abstract: An embodiment of the system operates in a parallel packet switch architecture having at least one egress adapter arranged to receive data packets issued from a plurality of ingress adapters and switched through a plurality of independent switching planes. Each received data packet belongs to one sequence of data packets among a plurality of sequences where the data packets are numbered with a packet sequence number (PSN) assigned according to at least a priority level of the data packet. Each data packet received by the at least one egress adapter has a source identifier to identify the ingress adapter from which it is issued. The system for restoring the sequences of the received data packets operates within the egress adapter and comprises buffer for temporarily storing each received data packet at an allocated packet buffer location, a controller, and a determination means coupled to a storing means and extracting means.Type: ApplicationFiled: May 20, 2008Publication date: October 30, 2008Inventors: Alain Blanc, Rene Glaise, Michel Poret, Rene Gallezot
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Publication number: 20080225854Abstract: A system for controlling egress buffer saturation includes, for each data packet flow, a comparator for comparing the number of data packets ‘WPC’ temporarily stored within an egress buffer to a predefined threshold value ‘WPCth’. The packet sequence number ‘PSNr’ of a last received in-sequence data packet and each highest packet sequence number ‘HPSNj’ received through respective ones of the plurality of switching planes is stored. By comparing the last received in-sequence packet sequence number ‘PSNr’ to each highest packet sequence number ‘HPSNj’ when the number of data packets ‘WPC’ exceeds the predefined threshold value ‘WPCth’ a determination as to which switching plane(s), among the plurality of switching planes, to unstop the flow of data packets can be made.Type: ApplicationFiled: May 23, 2008Publication date: September 18, 2008Applicant: International Business Machines CorporationInventors: Francois Le Maut, Rene Glaise, Michel Poret, Rene Gallezot
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Publication number: 20080172589Abstract: A method for combining a simple forward error correction code i.e., a Hamming-like code with scrambling and descrambling functions is disclosed. Therefore, irrespective of the information to be transported, received data may be corrected, bit error spreading effects being handled, while providing desirable signal characteristics such as signal DC balance and enough signal transitions. The overhead introduced by the method is a modest increase over the original overhead of the 10 Gb Ethernet 64B/66B code.Type: ApplicationFiled: July 11, 2007Publication date: July 17, 2008Inventors: Rene Gallezot, Rene Glaise, Michel Poret
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Patent number: 7400629Abstract: A system for resequencing data packets is disclosed. In a preferred embodiment, the system operates in a parallel packet switch architecture having at least one egress adapter arranged to receive data packets issued from a plurality of ingress adapters and switched through a plurality of independent switching planes. Each received data packet belongs to one sequence of data packets among a plurality of sequences where the data packets are numbered with a packet sequence number (PSN) assigned according to at least a priority level of the data packet. Each data packet received by the at least one egress adapter is further having a source identifier to identify the ingress adapter from which it is issued. The system for restoring the sequences of the received data packets operates within the egress adapter and comprises buffer for temporarily storing each received data packet at an allocated packet buffer location.Type: GrantFiled: November 26, 2003Date of Patent: July 15, 2008Assignee: International Business Machines CorporationInventors: Alain Blanc, Rene Glaise, Michel Poret, Rene Gallezot
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Patent number: 7391766Abstract: A system for controlling egress buffer saturation includes, for each data packet flow, a comparator for comparing the number of data packets ‘WPC’ temporarily stored within an egress buffer to a predefined threshold value ‘WPCth’. The packet sequence number ‘PSNr’ of a last received in-sequence data packet and each highest packet sequence number ‘HPSNj’ received through respective ones of the plurality of switching planes is stored. By comparing the last received in-sequence packet sequence number ‘PSNr’ to each highest packet sequence number ‘HPSNj’ when the number of data packets ‘WPC’ exceeds the predefined threshold value ‘WPCth’ a determination as to which switching plane(s), among the plurality of switching planes, to unstop the flow of data packets can be made.Type: GrantFiled: November 26, 2003Date of Patent: June 24, 2008Assignee: International Business Machines CorporationInventors: Francois Le Maut, Rene Glaise, Michel Poret, Rene Gallezot
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Patent number: 7385993Abstract: A queue scheduling mechanism in a data packet transmission system, the data packet transmission system including a transmission device for transmitting data packets, a reception device for receiving the data packets, a set of queue devices respectively associated with a set of priorities each defined by a priority rank for storing each data packet transmitted by the transmission device into the queue device corresponding to its priority rank and a queue scheduler for reading, at each packet cycle, a packet in one of the queue devices determined by a normal priority preemption algorithm. The queue scheduling mechanism includes a credit device that provides, at each packet cycle, a value N defining the priority rank to be read by the queue scheduler from the queue device corresponding to the priority N instead of the queue device determined by the normal priority preemption algorithm.Type: GrantFiled: November 21, 2002Date of Patent: June 10, 2008Assignee: International Business Machines CorporationInventors: Alain Blanc, Rene Gallezot, Francois Le Maut, Daniel Wind
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Patent number: 7382792Abstract: A queue scheduling mechanism in a data packet transmission system, the data packet transmission system including a transmission device for transmitting data packets, a reception device for receiving the data packets, a set of queue devices respectively associated with a set of priorities each defined by a priority rank for storing each data packet transmitted by the transmission device into the queue device corresponding to its priority rank, and a queue scheduler for reading, at each packet cycle, a packet in one of the queue devices determined by a normal priority preemption algorithm. The queue scheduling mechanism includes a credit device that provides at each packet cycle a value N defining the priority rank to be considered by the queue scheduler whereby a data packet is read by the queue scheduler from the queue device corresponding to the priority N instead of the queue device determined by the normal priority preemption algorithm.Type: GrantFiled: November 21, 2002Date of Patent: June 3, 2008Assignee: International Business Machines CorporationInventors: Alain Blanc, Bernard Brezzo, Rene Gallezot, Francois Le Mauf, Daniel Wind
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Patent number: 7324460Abstract: A method for controlling the flows of data packets that are switched or routed at nodes of high-speed communication networks is disclosed. According to the invention, resource metering units are assigned to resources shared between devices of the switch or router e.g., shared memories or link bandwidths. When the occupancy of a shared resource reaches a predetermined threshold, an event is generated and transmitted to devices sharing this resource. Furthermore, a periodic refresh of the overall flow control information is performed so that lost events are, however, eventually acted on. Thus, a new device may become active without perturbing the active flows after having gathered enough flow control information.Type: GrantFiled: September 29, 2003Date of Patent: January 29, 2008Assignee: International Business Machines CorporationInventors: Rene Gallezot, Rene Glaise, Francois Le Maut
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Publication number: 20080016510Abstract: A method for controlling the flows of data packets that are switched or routed at nodes of high-speed communication networks is disclosed. According to the invention, resource metering units are assigned to resources shared between devices of the switch or router e.g., shared memories or link bandwidths. When the occupancy of a shared resource reaches a predetermined threshold, an event is generated and transmitted to devices sharing this resource. Furthermore, a periodic refresh of the overall flow control information is performed so that lost events are, however, eventually acted on. Thus, a new device may become active without perturbing the active flows after having gathered enough flow control information.Type: ApplicationFiled: September 17, 2007Publication date: January 17, 2008Applicant: International Business Machines CorporationInventors: Rene Gallezot, Rene Glaise, Francois Le Maut
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Patent number: 7284184Abstract: A method for combining a simple forward error correction code i.e., a Hamming-like code with scrambling and descrambling functions is disclosed. Therefore, irrespective of the information to be transported, received data may be corrected, bit error spreading effects being handled, while providing desirable signal characteristics such as signal DC balance and enough signal transitions. The overhead introduced by the method is a modest increase over the original overhead of the 10 Gb Ethernet 64B/66B code.Type: GrantFiled: January 23, 2004Date of Patent: October 16, 2007Assignee: International Business Machines CorporationInventors: Rene Gallezot, Rene Glaise, Michel Poret
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Patent number: 7272778Abstract: A method and systems to test a communication system (200) comprising a plurality of emitters (205), receivers (210) and channels (220) are disclosed. According to the method of the invention the data used for the test are preprocessed so as to be analyzed on the fly by the receivers during the test. In a preferred embodiment, a connection identifier value characterizing emitter and receiver addresses as well as data properties, if any, is associated to each data and CRC bits are computed to format frames comprising data, connection identifier value and CRC bits (410). During the test, the communication system transmits frames from emitters to corresponding receivers. Upon frames reception, receivers extract data (455), connection identifier value (460) and CRC bits (465) and compute CRC bits on received data (470). The comparison (475) of transmitted and computed CRC bits in receiver allows determining whether or not frames have been well transmitted.Type: GrantFiled: September 5, 2003Date of Patent: September 18, 2007Assignee: International Business Machines CorporationInventors: Alain Blanc, Bruno Mesnet, Rene Gallezot
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Patent number: 7134067Abstract: The present invention describes direct decoding of Error Correction Codes (ECC) such as, for example, FIRE and similar codes, and detecting and correcting errors occurring in burst, without requiring any pattern shift or sequential logic. According to the present invention, the syndrome of a code generated with a degree-d polynomial is split into sub-syndromes that are combined to form at least one kind of error pattern from which an error pattern is picked. If the picked error pattern does not correspond to an uncorrectable error and errors are not confined within first d bits, one of the sub-syndromes is selected according to the correction mode. The ranks of this selected sub-syndrome and picked error pattern in the Galois field generated by a factor of the degree-d polynomial are determined.Type: GrantFiled: March 20, 2003Date of Patent: November 7, 2006Assignee: International Business Machines CorporationInventors: Rene Gallezot, Rene Glaise, Michel Poret
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Patent number: 7061909Abstract: A data switch is provided which routes fixed-size data packets from input ports to output ports, using shared memory which holds a copy of each packet in buffers. Output ports have a queue which contains pointers to buffers holding packets bound for that port. The number of shared memory buffers holding packets is compared to the number of buffer pointers in the output queues. In this way, a Multicast Index (MCI), a metric of the level of multicast traffic, is derived. The switch includes a Switch Core Adaptation Layer (SCAL) which has a multicast input queue. Because traffic is handled based on priority class P, a multicast threshold MCT(P), associated with the multicast input queue, is established per priority. While receiving traffic, the MCI is updated and, for each priority class in each SCAL, the MCI is compared to the MCT(P) to determine whether corresponding multicast traffic must be held.Type: GrantFiled: September 10, 2001Date of Patent: June 13, 2006Assignee: International Business Machines CorporationInventors: Alain Blanc, Bernard Brezzo, Rene Gallezot, Franco Le Maut, Thierry Roman, Daniel Wind
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Patent number: 6992980Abstract: The invention permits an effective traffic flow control, down to all sub-ports, of a switch made of a N-port core switch fabric. Sub-ports concentrate traffic from lower speed lines to a switch fabric native port. In each sub-port adapter, when congestion is detected in the OUT leg, it is reported through the corresponding IN leg. Congestion is piggybacked over the incoming traffic entering the input port of the N-port core switching fabric and is broadcast so that all sub-ports become aware of the detected congestion in any of the sub-ports. Each sub-port adapter performs a checking of the congestion status of all the other sub-ports and acts to stop forwarding received traffic destined for congested sub-ports and holds further received traffic until the sub-ports are reported to be no longer congested. The full intrinsic performance of a N-port switch fabric is realized by concentrating, through port and sub-port adapters, the traffic of more than N independent lines.Type: GrantFiled: June 19, 2001Date of Patent: January 31, 2006Assignee: International Business Machines CorporationInventors: Bernard Brezzo, Rene Gallezot, Francois Le Maut, Daniel Wind
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Publication number: 20040193997Abstract: A method for combining a simple forward error correction code i.e., a Hamming-like code with scrambling and descrambling functions is disclosed. Therefore, irrespective of the information to be transported, received data may be corrected, bit error spreading effects being handled, while providing desirable signal characteristics such as signal DC balance and enough signal transitions. The overhead introduced by the method is a modest increase over the original overhead of the 10 Gb Ethernet 64B/66B code.Type: ApplicationFiled: January 23, 2004Publication date: September 30, 2004Applicant: International Business Machines CorporationInventors: Rene Gallezot, Rene Glaise, Michel Poret