Abstract: The swapping function of input values to output values is performed through a pseudo content addressable memory which provides output values corresponding to a number E of n-bit input values, with E=2p−1. The pseudo content addressable memory is made of a plurality of cascaded random address memories 20 having at least a 2d addressing capability, with d higher than p. A control logic circuit is provided to store into each random access memory p-bits pointers, with each pointer being different from the others and randomly assigned to an input value.

Abstract: A method and apparatus for achieving the detection of triple errors and the correction of double errors in data stored in a memory or processed in a data processing system. The method and apparatus being based on a modification of a standard Bose Chauduri Hocquenghem (BCH) code that permits a reduction of the decoding circuitry needed to achieve the detection and correction of the errors.

Abstract: Described is a sequencing device comprising a plurality of shift register stages, a plurality of switches and an output bus which couples the outputs from the shift register stages to inputs of the switches. Each shift register stage includes a data input port coupled to a selected switch, a clock input port coupled to a clock control signal line and a clear input port coupled to a clear control signal line. The sequencing device may be set in at least one of a plurality of states by external events that are provided as input signals to the sequencing device through input bus (10).

Abstract: The bit configurations are arranged in M-bit code words, each word comprising a number D of data bits and an even number N of error correcting bits. The data bits are partitioned into N fields with an error correcting bit associated with each field to indicate the parity of the associated field. The assignment of data bits to the N fields in such that, when the N fields are used to generate an N-bit error syndrome, this syndrome will contain an odd number n1 of bits at a first value if there is a single bit in error, where N-n1=n2 is also odd, and an even number of bits different from N to indicate a two-bit error. The number of bits of the first value are then used to determine whether the codeword is in its true or inverted form.

Abstract: This specification describes a charge-transfer device transversal filter chip in which an input signal is fed in parallel into a number of channels the outputs of which are summed together to provide the desired transversal filter transfer function. Each channel contains an analog shift register, a signal splitter and a polarity selector. The shift registers are of unequal length to provide a different delay thru each channel. The signal splitter provides a plurality of signal paths thru each channel while the polarity selector determines whether a given path in a given channel is added or subtracted in the summation to determine the gain of the given channel in the summation.