Abstract: The invention relates to a microchip with a multiplicity of reconfigurable test structures, wherein the microchip has a test input (TDI) and a test output (TDO), wherein the multiplicity of test structures can be connected to the test input (TDI) and the test output (TDO), wherein one intermediate memory is provided for each of the multiplicity of test structures, wherein each of the multiplicity of test structures can be tested separately and concurrently with the aid of the respective intermediate memory and a corresponding individual control.

Abstract: The invention relates to a microchip with a multiplicity of reconfigurable test structures, wherein the microchip has a test input (TDI) and a test output (TDO), wherein the multiplicity of test structures can be connected to the test input (TDI) and the test output (TDO), wherein one intermediate memory is provided for each of the multiplicity of test structures, wherein each of the multiplicity of test structures can be tested separately and concurrently with the aid of the respective intermediate memory and a corresponding individual control.

Abstract: Disclosed are representative examples of methods, apparatus, and systems for generating test patterns targeting multiple faults using Boolean Satisfiability (SAT)-based test pattern generation methods. A SAT instance is constructed based on the circuit design information and a set of faults being targeted. A SAT solving engine is applied to the SAT instance to search for a test pattern for detecting the set of faults. The SAT instance or the SAT solving engine may be modified so that the SAT solving engine will search for a test pattern for detecting a maximum number of faults in the set of faults.

Abstract: On-chip logic includes a shadow register cross-coupled with a multiple input shift/signature register (MISR). The shadow register facilitates debugging by shifting out a test signature while resetting the MISR with a fault-free signature. The on-chip logic may further include comparator circuitry to produce an output signal by comparing the test signature with the fault-free signature or by first compressing the test signature and then comparing the compressed test signature with the compressed fault-free signature.

Abstract: Disclosed are representative examples of methods, apparatus, and systems for generating test patterns targeting multiple faults using Boolean Satisfiability (SAT)-based test pattern generation methods. A SAT instance is constructed based on the circuit design information and a set of faults being targeted. A SAT solving engine is applied to the SAT instance to search for a test pattern for detecting the set of faults. The SAT instance or the SAT solving engine may be modified so that the SAT solving engine will search for a test pattern for detecting a maximum number of faults in the set of faults.

Abstract: On-chip logic includes a shadow register cross-coupled with a multiple input shift/signature register (MISR). The shadow register facilitates debugging by shifting out a test signature while resetting the MISR with a fault-free signature. The on-chip logic may further include comparator circuitry to produce an output signal by comparing the test signature with the fault-free signature or by first compressing the test signature and then comparing the compressed test signature with the compressed fault-free signature.

Abstract: Cell-aware fault models directly address layout-based intra-cell defects. They are created by performing analog simulations on the transistor-level netlist of a library cell and then by library view synthesis. The cell-aware fault models may be used to generate cell-aware test patterns, which usually have higher defect coverage than those generated by conventional ATPG techniques. The cell-aware fault models may also be used to improve defect coverage of a set of test patterns generated by conventional ATPG techniques.