Abstract: A method of recovering from loading invalid data into a register within a pipelined processor. The method comprises the steps of (A) setting a register status for the register to an invalid state in response to loading invalid data into the register and (B) stalling the processor in response to an instruction requiring data buffered by the register and the register status being in the invalid state.

Abstract: A network interface unit which implements a low latency algorithm for buffer credit calculation. In one embodiment, a system network is provided with a remote node coupled to a local node by a serial communications link. The remote node is configured to transmit a data frame to the local node only if the remote node receives a buffer credit which indicates that the local node has available receive buffer space for a data frame. The local node includes a network interface unit for coupling to the serial communications link, and the network interface unit includes a receive buffer, a receive controller, a transmit controller, and a buffer credit manager. The receive controller stores incoming data frames in the receive buffer until they can be forwarded to the i/o bus of the local node. The transmit controller is configured to send buffer credits to the remote node in response to a credit signal from the buffer credit manager.