Abstract: A method is provided for increasing the efficiency of virtual machine processing. A parent virtual machine is provided on a host computer. The parent virtual machine is temporarily or permanently suspended. A child virtual machine is created at a new location by forking the parent virtual machine. The child virtual machine may not initially include all the stored data that is associated with the parent virtual machine.

Abstract: In accordance with certain aspects of the model-based policy application, each of a plurality of policies is associated with appropriate parts of a model of a heterogeneous system. A deployment agent is invoked to apply each of the plurality of policies to components associated with the parts of the model. An identification of a change to one of the plurality of policies is received, and the deployment agent is also invoked to apply the changed policy to selected ones of the components associated with the parts of the model.

Abstract: A method is provided for increasing the efficiency of virtual machine processing. A parent virtual machine is provided on a host computer. The parent virtual machine is temporarily or permanently suspended. A child virtual machine is created at a new location by forking the parent virtual machine. The child virtual machine may not initially include all the stored data that is associated with the parent virtual machine.

Abstract: In an emulated computing environment, a method is provided for licensing software of one or more guest computer systems. A license key server is provided in the host computer system for monitoring the initiation of unlicensed software, including operating system software, in the guest computer system. A determination is made by the license key server as to whether additional a license is available for each unlicensed software application. If a license is available, a license is granted and the count of available licenses is decremented. If a license is not available, a license is not granted and the unlicensed software application in the guest computer system is disabled.

Abstract: Enhanced shadow page table algorithms are presented for enhancing typical page table algorithms. In a virtual machine environment, where an operating system may be running within a partition, the operating system maintains it's own guest page tables. These page tables are not the real page tables that map to the real physical memory. Instead, the memory is mapped by shadow page tables maintained by a virtualing program, such as a hypervisor, that virtualizes the partition containing the operating system. Enhanced shadow page table algorithms provide efficient ways to harmonize the shadow page tables and the guest page tables. Specifically, by using tagged translation lookaside buffers, batched shadow page table population, lazy flags, and cross-processor shoot downs, the algorithms make sure that changes in the guest pages tables are reflected in the shadow page tables.

Abstract: Efficient power management of a system with virtual machines is disclosed. In particular, such efficient power management may enable coordination of system-wide power changes with virtual machines. Additionally, such efficient power management may enable coherent power changes in a system with a virtual machine monitor. Furthermore, such efficient power management may enable dynamic control and communication of power state changes.

Abstract: An operating system is described that is capable of ascertaining whether it is executing in a virtual machine environment and is further capable of modifying its behavior to operate more efficiently and provide optimal behavior in a virtual machine environment. An operating system is enlightened so that it is aware of VMMs or hypervisors, taking on behavior that is optimal to that environment. The VMM or hypervisor informs the operating system of the optimal behavior, and vice versa.

Abstract: A catch-up mode that runs a virtual programmable interrupt timer faster than a nominal rate to prevent time loss in a virtual machine can be implemented. If time loss is determined, a catch-up mode can be initiated to cause increased firings, beyond a nominal rate, of the programmable interrupt timer to adjust the clock of the virtual machine to the clock of the host system. The virtual programmable interrupt timer can also be readjusted to a predetermined nominal rate when the time loss in the guest operating system is determined approximately within a predetermined tolerance range. The catch-up mode can be monitored to avoid “interrupt storms” on the virtual machine. The virtual programmable interrupt timer can be altered by the guest operating system to accommodate different operating systems.

Abstract: Model-based virtual system provisioning includes accessing a model of a workload to be installed on a virtual machine of a system as well as a model of the system. A workload refers to some computing that is to be performed, and includes an application to be executed to perform the computing, and optionally includes the operating system on which the application is to be installed. The workload model identifies a source of the application and operating system of the workload, as well as constraints of the workload, such as resources and/or other capabilities that the virtual machine(s) on which the workload is to be installed must have. An installation specification for the application is also generated, the installation specification being derived at least in part from the model of the workload and the model of the virtual system.

Abstract: In an emulated computing environment, a method is provided for allocating resources of the host computer system among multiple virtual machines resident on the host computer system. On the basis of the proportional weight of each virtual machine, a proportional share of resources is allocated for each virtual machine. If, for a particular virtual machine, the calculated share is less than a reserved minimum share, the virtual machine is allocated its reserved minimum share as its share of processor resources. An emulation program modulates the access of each virtual machine to the resources of the host computer system.

Abstract: Enhanced shadow page table algorithms are presented for enhancing typical page table algorithms. In a virtual machine environment, where an operating system may be running within a partition, the operating system maintains it's own guest page tables. These page tables are not the real page tables that map to the real physical memory. Instead, the memory is mapped by shadow page tables maintained by a virtualing program, such as a hypervisor, that virtualizes the partition containing the operating system. Enhanced shadow page table algorithms provide efficient ways to harmonize the shadow page tables and the guest page tables. Specifically, by using tagged translation lookaside buffers, batched shadow page table population, lazy flags, and cross-processor shoot downs, the algorithms make sure that changes in the guest pages tables are reflected in the shadow page tables.

Abstract: A method of virtualizing memory through shadow page tables that cache translations from multiple guest address spaces in a virtual machine includes a software version of a hardware tagged translation look-aside buffer. Edits to guest page tables are detected by intercepting the creation of guest-writable mappings to guest page tables with translations cached in shadow page tables. The affected cached translations are marked as stale and purged upon an address space switch or an indiscriminate flush of translations by the guest. Thereby, non-stale translations remain cached but stale translations are discarded. The method includes tracking the guest-writable mappings to guest page tables, deferring discovery of such mappings to a guest page table for the first time until a purge of all cached translations when the number of untracked guest page tables exceeds a threshold, and sharing shadow page tables between shadow address spaces and between virtual processors.

Abstract: Various embodiments of the present invention are directed to augmented interrupt controllers (AICs) and to synthetic interrupt sources (SISS) providing richer interrupt information (or “synthetic interrupts” or “SIs”). The AIC and SIS provide efficient means for sending and receiving interrupts, and particularly interrupts sent to and received by virtual machines. Several of these embodiments are specifically directed to an interrupt controller that is extended to accept and deliver additional information associated with an incoming interrupt. For certain such embodiments, a memory-mapped extension to the interrupt controller includes a data structure that is populated with the additional information as part of the interrupt delivery. Although several of the embodiments described herein are disclosed in the context of a virtual machine system, the inventions disclosed herein can also be applied to traditional computer systems (without a virtualization layer) as well.

Abstract: Various embodiments of the present invention are directed to a multi-level virtualizer that is designed to remove much of the intercept-related functionality from the base-level virtualizer (that exists outside of each partition) and, instead, incorporate much of this functionality directly into each partition. For several of the embodiments, certain intercept handling functions are performed by an “external monitor” that runs within a partition and responds to specific intercept events, and the base-level virtualizer installs these external monitors within each partition and thereafter manages the external monitors for both single-partition and cross-partition intercept events. This distributed approach to intercept handling allows for a much less complex virtualizer and moves the intercept functionality up into each partition where each external monitor uses the resources of the corresponding guest operating system in that partition to resolve the intercept event.

Abstract: A method of performing a translation from a guest virtual address to a host physical address in a virtual machine environment includes receiving a guest virtual address from a host computer executing a guest virtual machine program and using the hardware oriented method of the host CPU to determine the guest physical address. A second level address translation to a host physical address is then performed. In one embodiment, a multiple tier tree is traversed which translates the guest physical address into a host physical address. In another embodiment, the second level of address translation is performed by employing a hash function of the guest physical address and a reference to a hash table. One aspect of the invention is the incorporation of access overrides associated with the host physical address which can control the access permissions of the host memory.

Abstract: The present invention is directed to making a guest operating system aware of the topology of the subset of host resources currently assigned to it. At virtual machine boot time a Static Resource Affinity Table (SRAT) will be used by the virtualizer to group guest physical memory and guest virtual processors into virtual nodes. Thereafter, in one embodiment, the host physical memory behind a virtual node can be changed by the virtualizer as necessary, and the virtualizer will provide physical processors appropriate for the virtual processors in that node.

Abstract: In a virtual computing machine, a system and method that dynamically patches the interrupt mechanism (in interrupt vector space) of a host computing architecture with guest mode software. Significant increases in performance are achieved without depending on the host code. A patching mechanism evaluates the operating system version, processor, and code to be patched. If patchable, low-level interfaces are created dynamically; a dispatcher is written into an unused location in vector space, and instructions copied from each interrupt vector to be patched to a guest interrupt vector. For an interrupt, the new, patched instructions branch to the dispatcher, which then branches to the appropriate patched interrupt guest code. If the processor is operating as a virtual machine, the guest interrupt code handles the interrupt, otherwise the original copied instructions are replayed, followed by execution at the original host instruction in vector space that exists after the copied and patched instructions.

Abstract: Model-based provisioning of test environments includes accessing a model of an application to be installed in a test environment of a system and further accessing a model of the system and a model of the test environment. An installation specification for the application is also generated, the installation specification being derived at least in part from the model of the application, the model of the system, and the model of the test environment.

Abstract: A model of a system is generated and used as a basis for managing the system. As the system is managed, the system model can be updated to reflect changes to the system. Managing of the system can include one or more of provisioning applications in the system, provisioning applications in virtual systems, provisioning test environments, monitoring the configuration of the system, monitoring the system including the health of the system, performing capacity planning for the system, and propagating attributes to different components in the system.

Abstract: The present invention provides a virtualized computing systems and methods for transitioning in real time between LONG SUPER-MODE and LEGACY SUPER-MODE in the x86-64 architecture. In doing so, a virtual machine, which relies on the traditional 32-bit modes, i.e., REAL MODE and PROTECTED MODE (V86 SUB-MODE, RING-0 SUB-MODE, and RING-3 SUB-MODE), is able to run alongside other applications on x86-64 computer hardware (i.e., 64-bit). The method of performing a temporary processor mode context switch includes the steps of the virtual machine monitor's setting up a “virtual=real” page, placing the transition code for performing the processor mode context switch on this page, jumping to this page, disabling the memory management unit (MMU) of the x86-64 computer hardware, modifying the mode control register to set either the LONG SUPER-MODE bit or LEGACY SUPER-MODE bit, loading a new page table, and reactivating the MMU of the x86-64 computer hardware.