Abstract: A driver for a semiconductor chip, the driver having a drain wire with a first end and a second end and p and n-type transistors each with a source, gate and drain. The source of the p-type transistors connected to a positive power supply line, the source of the n-type transistors connected to a ground power supply line. The gates of the p and n-type transistors connected to a first and second input signals respectively. The drains of the p and n-type transistors connected to the drain wire. The p and n-type transistors arranged so that a difference between a number of n-type transistors connected to the drain wire and a number of p-type transistors connected to the drain wire between the first end of the drain wire and all distances along the drain wire being less than two.

Abstract: A system includes a computer readable storage medium and a processor. The computer readable storage includes data representing an input/output (“I/O”) cell of a first type for modeling and/or fabricating a semiconductor device. The I/O cell of the first type includes circuitry for providing a first plurality of functions. The processor is in communication with the computer readable storage medium and is configured to select the I/O cell of the first type, arrange a plurality of the I/O cells of the first type on a model of an semiconductor device, and store the model of the semiconductor device including the plurality of the I/O cells of the first type in the computer readable storage medium.

Abstract: A driver for a semiconductor chip, the driver having a drain wire with a first end and a second end and p and n-type transistors each with a source, gate and drain. The source of the p-type transistors connected to a positive power supply line, the source of the n-type transistors connected to a ground power supply line. The gates of the p and n-type transistors connected to a first and second input signals respectively. The drains of the p and n-type transistors connected to the drain wire. The p and n-type transistors arranged so that a difference between a number of n-type transistors connected to the drain wire and a number of p-type transistors connected to the drain wire between the first end of the drain wire and all distances along the drain wire being less than two.

Abstract: A system includes a computer readable storage medium and a processor. The computer readable storage includes data representing an input/output (“I/O”) cell of a first type for modeling and/or fabricating a semiconductor device. The I/O cell of the first type includes circuitry for providing a first plurality of functions. The processor is in communication with the computer readable storage medium and is configured to select the I/O cell of the first type, arrange a plurality of the I/O cells of the first type on a model of an semiconductor device, and store the model of the semiconductor device including the plurality of the I/O cells of the first type in the computer readable storage medium.

Abstract: In general, in one aspect, the disclosure describes an apparatus for calibrating signals. The apparatus includes a receiver pair to receive a differential signal and a reference signal and to generate at least one comparison signal reflecting where a first signal of the differential signal and a second signal of the differential signal cross each other with respect to the reference signal. The second signal is a negative compliment of the first signal. The apparatus further includes a phase detector to determine a phase error based on the at least one comparison signal. The apparatus also includes an edge delay control driver pair to adjust the differential signal based on the phase error.

Abstract: In general, in one aspect, the disclosure describes an apparatus for calibrating signals. The apparatus includes a receiver pair to receive a differential signal and a reference signal and to generate at least one comparison signal reflecting where a first signal of the differential signal and a second signal of the differential signal cross each other with respect to the reference signal. The second signal is a negative compliment of the first signal. The apparatus further includes a phase detector to determine a phase error based on the at least one comparison signal. The apparatus also includes an edge delay control driver pair to adjust the differential signal based on the phase error.