Abstract: A plurality of computer stations each includes a data processing computer capable of having its data processing function inhibited or halted by a halt signal applied to a halt input terminal, and each also includes a random access memory (RAM). The plurality of computer stations are interconnected by a bus system and controlled by a bus controller for allowing the periodic interchange of data among the random access memories of the computer stations. The bus controller periodically generates a halt signal which is applied in common to the halt input terminal of each computer station and which stops the processing of data by each data processing computer during the interchange of data. During the time of each halt signal, the bus controller generates in time sequence computer station address signals which are applied in common over the bus system to an address decoder associated with each computer station.