Abstract: An apparatus can include processor cores and control circuitry coupled to the processor cores. The control circuitry can detect at least one of a power characteristic and a frequency characteristic of at least one of the processor cores. The control circuitry can determine that a frequency control opportunity is present on at least one of the processor cores based on at least one of the power characteristic and the frequency characteristic. The control circuitry can adjust a power parameter of at least one of the processor cores responsive to determining that the frequency control opportunity is present.

Abstract: An accelerator device determines a compression format based on a header of a structured data element to be decompressed. The accelerator device may configure the accelerator device based on the compression format. The accelerator device may decompress a data block of the structured data element based on the configuration.

Abstract: An inlet assembly for a housing containing an aftertreatment component of an aftertreatment system comprises an inlet conduit configured to be disposed substantially perpendicular to a longitudinal axis of the housing. A flow redirection conduit is disposed downstream of the inlet conduit and is coupled to the end of the housing. A plurality of protrusions project from a sidewall of the flow redirection conduit towards an inlet face of the aftertreatment component and are configured to provide a uniform exhaust gas flow to the inlet face. Alternatively, a flow distribution plate having a plurality of slots defined substantially perpendicular to the longitudinal axis is disposed in the flow redirection conduit, the plate being inclined with respect to the longitudinal axis. The slots are configured to provide a uniform exhaust gas flow to the inlet face.

Abstract: Examples include techniques for monitoring a data packet transfer rate at an interface queue, and based at least in part on a comparison of the data packet transfer rate to a threshold, assigning the interface queue from a core of a first class to a core of a second class or assigning the interface queue from a core of the second class to a core of the first class.

Abstract: Technologies for dynamic multi-core packet processing distribution include a compute device having a distributor core, a direct memory access (DMA) engine, and multiple worker cores. The distributor core writes work data to a distribution buffer. The work data is associated with a packet processing operation. The distributor core may perform a work distribution operation to generate the work data. The work data may be written to a private cache of the distributor core. The distributor core programs the DMA engine to copy the work data from the distribution buffer to a shadow buffer. The DMA engine may copy the work data from one cache line of a shared cache to another cache line of the shared cache. The worker cores access the work data in the shadow buffer. The worker cores may perform the packet processing operation with the work data. Other embodiments are described and claimed.

Abstract: Technologies for dynamic multi-core packet processing distribution include a compute device having a distributor core, a direct memory access (DMA) engine, and multiple worker cores. The distributor core writes work data to a distribution buffer. The work data is associated with a packet processing operation. The distributor core may perform a work distribution operation to generate the work data. The work data may be written to a private cache of the distributor core. The distributor core programs the DMA engine to copy the work data from the distribution buffer to a shadow buffer. The DMA engine may copy the work data from one cache line of a shared cache to another cache line of the shared cache. The worker cores access the work data in the shadow buffer. The worker cores may perform the packet processing operation with the work data. Other embodiments are described and claimed.

Abstract: Examples include techniques for monitoring a data packet transfer rate at an interface queue, and based at least in part on a comparison of the data packet transfer rate to a threshold, assigning the interface queue from a core of a first class to a core of a second class or assigning the interface queue from a core of the second class to a core of the first class.