Abstract: A device for testing the fixability of logic circuits having an embedded memory. The logic circuit includes a built-in test circuit for generating data which tests the embedded memory. An allocation logic circuit provides an output line for each bit of the memory identifying if the bit has either failed or passed. A Failed Data Bit Register is connected to the output lines. The Failed Data Bit Register includes a plurality of shift register stages. A multiplex circuit associated with each stage of the shift register receives as a first input the corresponding output line of the allocation logic circuit. A second input of the multiplex circuit connects to the preceding stage of the shift register. A clock cycle counter connects to an enabling line of the multiplex circuits and to a source of clock pulses.

Abstract: An integrated chip having a DRAM embedded in logic is tested by an in-situ processor oriented BIST macro. The BIST is provided with two ROMS, one for storing test instructions and a second, which is scannable, that provides sequencing for the test instructions stored in the first ROM, as well as branching and looping capabilities. The BIST macro has, in addition, a redundancy allocation logic section for monitoring failures within the DRAM and for replacing failing word and/or data lines. By stacking the DRAM in 0.5 mb increments up to a 4.0 mb maximum or in 1.0 mb increments up to an 8 mb maximum, all of which are controlled and tested by the BIST macro, a customized chip design with a high level of granularity can be achieved and tailored to specific applications within a larger ASIC.