Patents by Inventor Rex Stone
Rex Stone has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9059115Abstract: Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.Type: GrantFiled: December 4, 2013Date of Patent: June 16, 2015Assignee: Micron Technology, Inc.Inventors: David A. Kewley, Brian Cleereman, Stephen W. Russell, Rex Stone, Anthony C. Krauth
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Publication number: 20140087558Abstract: Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.Type: ApplicationFiled: December 4, 2013Publication date: March 27, 2014Applicant: Micron Technology, Inc.Inventors: David A. Kewley, Brian Cleereman, Stephen W. Russell, Rex Stone, Anthony C. Krauth
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Patent number: 8609489Abstract: Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.Type: GrantFiled: June 6, 2011Date of Patent: December 17, 2013Assignee: Micron Technology, Inc.Inventors: David A. Kewley, Brian Cleereman, Stephen W. Russell, Rex Stone, Anthony C. Krauth
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Publication number: 20110237081Abstract: Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.Type: ApplicationFiled: June 6, 2011Publication date: September 29, 2011Applicant: MICRON TECHNOLOGY, INC.Inventors: David A. Kewley, Brian Cleereman, Stephen W. Russell, Rex Stone, Anthony C. Krauth
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Patent number: 7972926Abstract: Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.Type: GrantFiled: July 2, 2009Date of Patent: July 5, 2011Assignee: Micron Technology, Inc.Inventors: David A. Kewley, Brian Cleereman, Stephen W. Russell, Rex Stone, Anthony C. Krauth
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Publication number: 20110003469Abstract: Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.Type: ApplicationFiled: July 2, 2009Publication date: January 6, 2011Inventors: David A. Kewley, Brian Cleereman, Stephen W. Russell, Rex Stone, Anthony C. Krauth
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Patent number: 6943071Abstract: A nonvolatile memory cell comprising a pair of spaced apart shallow trench isolation regions formed in a substrate and defining a substrate active region. A tunnel dielectric is formed on the substrate active region. A floating gate is formed on the tunnel dielectric and is self aligned between the spaced apart shallow trench isolation regions. A dielectric layer is formed on the floating gate and a control gate formed on the dielectric layer. A source region and a drain region are formed in the substrate active region on opposite sides of the floating gate.Type: GrantFiled: June 3, 2002Date of Patent: September 13, 2005Assignee: Intel CorporationInventors: Albert Fazio, Krishna Parat, Glen Wada, Neal Mielke, Rex Stone
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Patent number: 6518618Abstract: A nonvolatile memory cell comprising a pair of spaced apart shallow trench isolation regions formed in a substrate and defining a substrate active region. A tunnel dielectric is formed on the substrate active region. A floating gate is formed on the tunnel dielectric and is self aligned between the spaced apart shallow trench isolation regions. A dielectric layer is formed on the floating gate and a control gate formed on the dielectric layer. A source region and a drain region are formed in the substrate active region on opposite sides of the floating gate.Type: GrantFiled: December 3, 1999Date of Patent: February 11, 2003Assignee: Intel CorporationInventors: Albert Fazio, Krishna Parat, Glen Wada, Neal Mielke, Rex Stone
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Publication number: 20020149050Abstract: A nonvolatile memory cell comprising a pair of spaced apart shallow trench isolation regions formed in a substrate and defining a substrate active region. A tunnel dielectric is formed on the substrate active region. A floating gate is formed on the tunnel dielectric and is self aligned between the spaced apart shallow trench isolation regions. A dielectric layer is formed on the floating gate and a control gate formed on the dielectric layer. A source region and a drain region are formed in the substrate active region on opposite sides of the floating gate.Type: ApplicationFiled: June 3, 2002Publication date: October 17, 2002Inventors: Albert Fazio, Krishna Parat, Glen Wada, Neal Mielke, Rex Stone