Patents by Inventor Reynante Alvarado
Reynante Alvarado has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9425160Abstract: Wafer-level package (semiconductor) devices are described that have a reinforcement layer formed on an adhesion layer and/or a semiconductor substrate and covering at least a portion of at least one solder bump. Additionally, the reinforcement layer may cover at least a portion of a semiconductor device (e.g., a die) mounted on the semiconductor substrate. In an implementation, the wafer-level package (semiconductor) device may include an integrated circuit chip with an attached die, where the integrated circuit chip has at least one solder bump formed thereon with a reinforcement layer formed on a surface of the integrated circuit chip, where the reinforcement layer embeds the die and covers a portion of the at least one solder bump.Type: GrantFiled: March 14, 2013Date of Patent: August 23, 2016Assignee: Maxim Integrated Products, Inc.Inventors: Reynante Alvarado, Yi-Sheng A. Sun, Arkadii V. Samoilov, Yong L. Xu
-
Patent number: 9159684Abstract: A wafer-level packaged semiconductor device is described. In an implementation, the device includes one or more self-assembled resilient leads disposed on an integrated circuit chip. Each of the resilient leads are configured to move from a first position wherein the resilient lead is held adjacent to the chip and a second position wherein the resilient lead is extended away from the chip to interconnect the chip to a printed circuit board. A guard is provided to protect the resilient leads when the resilient leads are in the first position. One or more attachment bumps may also be furnished to facilitate attachment of the device to the printed circuit board.Type: GrantFiled: April 7, 2014Date of Patent: October 13, 2015Assignee: Maxim Integrated Products, Inc.Inventors: Chiung C. Lo, Arkadii V. Samoilov, Reynante Alvarado
-
Patent number: 8686560Abstract: Wafer-level chip-scale package semiconductor devices are described that have bump assemblies configured to mitigate solder bump failures due to stresses, particularly stresses caused by CTE mismatch during thermal cycling tests, dynamic deformation during drop tests or cyclic bending tests, and so on. In an implementation, the wafer-level chip-scale package devices include an integrated circuit chip having two or more arrays of bump assemblies for mounting the device to a printed circuit board. At least one of the arrays includes bump assemblies that are configured to withstand higher levels of stress than the bump assemblies of the remaining arrays.Type: GrantFiled: April 7, 2010Date of Patent: April 1, 2014Assignee: Maxim Integrated Products, Inc.Inventors: Pirooz Parvarandeh, Reynante Alvarado, Chiung C. Lo, Arkadii V. Samoilov
-
Patent number: 8446019Abstract: A semiconductor package includes a device pad on a substrate. A first polymer layer overlies the substrate, and the first polymer layer has an opening to expose the device pad. In one embodiment, a redistribution layer (RDL) comprises a landing pad, and the RDL is positioned on the first polymer layer and conductively coupled to the device pad. A second polymer layer is on the RDL, and an under bump metal pad (UBM) is on the landing pad and extends onto a top surface of the second polymer layer. In one embodiment, a shortest distance from a center of the landing pad to an outer edge of the landing pad, and a shortest distance from a center of the UBM to an outer edge of the UBM are in a ratio that ranges from 0.5:1 up to 0.95:1.Type: GrantFiled: April 26, 2012Date of Patent: May 21, 2013Assignee: Flipchip International, LLCInventors: Reynante Alvarado, Yuan Lu, Richard Redburn
-
Patent number: 8278748Abstract: A wafer-level packaged semiconductor device is described. In an implementation, the device includes one or more self-assembled resilient leads disposed on an integrated circuit chip. Each of the resilient leads are configured to move from a first position wherein the resilient lead is held adjacent to the chip and a second position wherein the resilient lead is extended away from the chip to interconnect the chip to a printed circuit board. A guard is provided to protect the resilient leads when the resilient leads are in the first position. One or more attachment bumps may also be furnished to facilitate attachment of the device to the printed circuit board.Type: GrantFiled: February 17, 2010Date of Patent: October 2, 2012Assignee: Maxim Integrated Products, Inc.Inventors: Chiung C. Lo, Arkadii V. Samoilov, Reynante Alvarado
-
Publication number: 20120228765Abstract: A semiconductor package includes a device pad on a substrate. A first polymer layer overlies the substrate, and the first polymer layer has an opening to expose the device pad. In one embodiment, a redistribution layer (RDL) comprises a landing pad, and the RDL is positioned on the first polymer layer and conductively coupled to the device pad. A second polymer layer is on the RDL, and an under bump metal pad (UBM) is on the landing pad and extends onto a top surface of the second polymer layer. In one embodiment, a shortest distance from a center of the landing pad to an outer edge of the landing pad, and a shortest distance from a center of the UBM to an outer edge of the UBM are in a ratio that ranges from 0.5:1 up to 0.95:1.Type: ApplicationFiled: April 26, 2012Publication date: September 13, 2012Applicant: FlipChip International, LLCInventors: Reynante Alvarado, Yuan Lu, Richard Redburn
-
Patent number: 8188606Abstract: A semiconductor package includes a device pad on a substrate. A polybenzoxazole (PBO) layer overlies the substrate, and the PBO layer has an opening to expose the device pad. A redistribution layer (RDL) comprises a landing pad, and the RDL is positioned on the PBO layer and conductively coupled to the device pad. A polymer layer is on the RDL, and an under bump metal pad (UBM) is on the landing pad and extends onto a top surface of the polymer layer. The UBM electrically connects to the landing pad through an opening in the polymer layer. A solder bump is secured to the UBM. A shortest distance from a center of the landing pad to an outer edge of the landing pad, and a shortest distance from a center of the UBM to an outer edge of the UBM are in a ratio that ranges from 0.5:1 up to 0.95:1.Type: GrantFiled: April 13, 2011Date of Patent: May 29, 2012Assignee: Flipchip International, LLCInventors: Reynante Alvarado, Yuan Lu, Richard Redburn
-
Publication number: 20110248398Abstract: Wafer-level chip-scale package semiconductor devices are described that have bump assemblies configured to mitigate solder bump failures due to stresses, particularly stresses caused by CTE mismatch during thermal cycling tests, dynamic deformation during drop tests or cyclic bending tests, and so on. In an implementation, the wafer-level chip-scale package devices include an integrated circuit chip having two or more arrays of bump assemblies for mounting the device to a printed circuit board. At least one of the arrays includes bump assemblies that are configured to withstand higher levels of stress than the bump assemblies of the remaining arrays.Type: ApplicationFiled: April 7, 2010Publication date: October 13, 2011Applicant: Maxim Integrated Products, Inc.Inventors: PIROOZ PARVARANDEH, Reynante Alvarado, Chiung C. Lo, Arkadii V. Samoilov
-
Publication number: 20110186995Abstract: A semiconductor package includes a device pad on a substrate. A polybenzoxazole (PBO) layer overlies the substrate, and the PBO layer has an opening to expose the device pad. A redistribution layer (RDL) comprises a landing pad, and the RDL is positioned on the PBO layer and conductively coupled to the device pad. A polymer layer is on the RDL, and an under bump metal pad (UBM) is on the landing pad and extends onto a top surface of the polymer layer. The UBM electrically connects to the landing pad through an opening in the polymer layer. A solder bump is secured to the UBM. A shortest distance from a center of the landing pad to an outer edge of the landing pad, and a shortest distance from a center of the UBM to an outer edge of the UBM are in a ratio that ranges from 0.5:1 up to 0.95:1.Type: ApplicationFiled: April 13, 2011Publication date: August 4, 2011Applicant: FlipChip International, LLCInventors: Reynante Alvarado, Yuan Lu, Richard Redburn
-
Patent number: 7973418Abstract: An apparatus and method for a semiconductor package including a bump on input-output (IO) structure are disclosed involving a device pad, an under bump metal pad (UBM), a polymer, and a passivation layer. The shortest distance from the center of the device pad to its outer edge, and the shortest distance from the center of the UBM to its outer edge are in a ratio from 0.5:1 to 0.95:1. Also, the shortest distance from the center of the polymer to its outer edge, and the shortest distance from the center of the UBM to its outer edge are in a ratio from 0.35:1 to 0.85:1. Additionally, the shortest distance from the center of the passivation layer to its outer edge, and the shortest distance from the center of the UBM to its outer edge are in a ratio from 0.35:1 to 0.80:1.Type: GrantFiled: April 21, 2008Date of Patent: July 5, 2011Assignee: Flipchip International, LLCInventors: Reynante Alvarado, Yuan Lu, Richard Redburn
-
Publication number: 20080308934Abstract: An apparatus and method for a semiconductor package including a bump on input-output (IO) structure are disclosed involving a device pad, an under bump metal pad (UBM), a polymer, and a passivation layer. The shortest distance from the center of the device pad to its outer edge, and the shortest distance from the center of the UBM to its outer edge are in a ratio from 0.5:1 to 0.95:1. Also, the shortest distance from the center of the polymer to its outer edge, and the shortest distance from the center of the UBM to its outer edge are in a ratio from 0.35:1 to 0.85:1. Additionally, the shortest distance from the center of the passivation layer to its outer edge, and the shortest distance from the center of the UBM to its outer edge are in a ratio from 0.35:1 to 0.80:1.Type: ApplicationFiled: April 21, 2008Publication date: December 18, 2008Applicant: FlipChip International, LLCInventors: Reynante Alvarado, Yuan Lu, Richard Redburn