Abstract: Disclosed is a pseudo static random access memory (PSRAM) and a method for operating the same. The PSRAM includes a multi-bit control register and a multiplexer circuit operatively coupled to the multi-bit control register. The multi-bit control register has a first set of bits reserved for a page control mode of the PSRAM and a second set of bits reserved for a bus control mode of the PSRAM. The multiplexer circuit activates one of the page control mode and the bus control mode of the PSRAM based on a logic level of an address bit inputted to the multiplexer circuit.

Abstract: One embodiment includes a dynamic memory operable in different refresh modes including an autonomous refresh mode in which the refresh rate is set by an internal self refresh timer circuit on the memory circuit die, and a test refresh mode in which the refresh rate is set by a timer circuit external to the memory circuit die. Other embodiments are described and claimed.

Abstract: Disclosed is a pseudo static random access memory (PSRAM) and a method for operating the same. The PSRAM includes a multi-bit control register and a multiplexer circuit operatively coupled to the multi-bit control register. The multi-bit control register has a first set of bits reserved for a page control mode of the PSRAM and a second set of bits reserved for a bus control mode of the PSRAM. The multiplexer circuit activates one of the page control mode and the bus control mode of the PSRAM based on a logic level of an address bit inputted to the multiplexer circuit.

Abstract: One embodiment includes a dynamic memory operable in different refresh modes including an autonomous refresh mode in which the refresh rate is set by an internal self refresh timer circuit on the memory circuit die, and a test refresh mode in which the refresh rate is set by a timer circuit external to the memory circuit die. Other embodiments are described and claimed.

Abstract: In some embodiments, a design for test feature to improve DRAM charge retention yield is presented. In this regard, an apparatus is introduced comprising a first integrated circuit die, and a second integrated circuit die stacked together in a package, wherein the second integrated circuit die comprises a dynamic random access memory (DRAM) and circuitry to increase a refresh rate provided by a self refresh timer by a predetermined percentage. Other embodiments are also disclosed and claimed.