Abstract: A GPS baseband architecture provides flexibility and power consumption and chip area usage advantages. The GPS baseband architecture includes a first stage having a preamplifier coupled to a low noise amplifier, which is coupled to a mixer. A PLL provides the mixer with a frequency to convert a signal to a higher intermediate (IF) frequency. The output of the mixer is fed to a poly-phase filter. The output of the poly-phase filter is fed to a programmable gain amplifier (PGA), whose output is fed to an analog-to-digital converter (ADC) to produce an output GPS signal. A saturation bit of the ADC is used to control the PGA through a digital amplifier gain control (AGC) circuit.

Abstract: A GPS baseband architecture provides flexibility and power consumption and chip area usage advantages. The GPS baseband architecture includes a first stage having a preamplifier coupled to a low noise amplifier, which is coupled to a mixer. A PLL provides the mixer with a frequency to convert a signal to a higher intermediate (IF) frequency. The output of the mixer is fed to a poly-phase filter. The output of the poly-phase filter is fed to a programmable gain amplifier (PGA), whose output is fed to an analog-to-digital converter (ADC) to produce an output GPS signal. A saturation bit of the ADC is used to control the PGA through a digital amplifier gain control (AGC) circuit.

Abstract: A GPS baseband architecture provides flexibility and power consumption and chip area usage advantages. The GPS baseband architecture includes a first stage having a preamplifier coupled to a low noise amplifier, which is coupled to a mixer. A PLL provides the mixer with a frequency to convert a signal to a higher intermediate (IF) frequency. The output of the mixer is fed to a poly-phase filter. The output of the poly-phase filter is fed to a programmable gain amplifier (PGA), whose output is fed to an analog-to-digital converter (ADC) to produce an output GPS signal. A saturation bit of the ADC is used to control the PGA through a digital amplifier gain control (AGC) circuit.

Abstract: The present invention discloses a mixer comprising with an input stage (100) for receiving and amplifying input signals (VINP, VINN) and an output stage (300) for outputting output signals (Voutp, Voutn). A switching stage (200) is coupled between the input stage (100) and the output stage (300), the switching stage (200) mixing the amplified input signals with a local oscillator signal (vlop, vlon) to produce the output signals (Voutp, Voutn) at the output stage (300). An RC circuit (cop, rop; con, ron) is connected to the output stage (300) and adapted to move the pole of the output signals.

Abstract: The present invention discloses an automatic gain controller with an amplifier (10) having an amplifier output connected to a mixer (20) and a receiver signal strength indicator (100) connected to the amplifier output and to a first counter (60). The first counter (60) is adapted to produce a signal to control gain of the amplifier (10) and receives its input from the receiver signal strength indicator (100) which causes the first counter (60) to count up or down depending on the strength of the signal output from the amplifier (10). The automatic gain controller also includes a second counter (70) which is connected to an applications circuit and is adapted to produce a signal to control gain of the mixer (20). The second counter (70) receives its input from a gain control signal from the applications circuit (50) and also from the first counter (60).

Abstract: The invention teaches an amplifier (100) with an input signal (IN) coupled to the gate of a second transistor (Q2) and an output signal (OUT) coupled to an output node between a third resistor (R3) and the drain of the second transistor (Q2). A third transistor (Q3) is coupled in parallel between the output node and the gate of a second transistor (Q2). A first bias signal (Vbias) is coupled to the output node and the gate of the third transistor (Q3). The amplifier preferably also includes a plurality of switchable resistors coupled to the output node to adjust the output for process variations. The invention also describes a method of compensating for process variations in an output of an amplifier which comprises producing a reference signal dependent on the difference between a reference value and an actual value and switching one or more resistors into the output of the amplifier to adjust the output of the amplifier to reflect the process variations.

Abstract: A GPS baseband architecture provides flexibility and power consumption and chip area usage advantages. The GPS baseband architecture includes a first stage having a preamplifier coupled to a low noise amplifier, which is coupled to a mixer. A PLL provides the mixer with a frequency to convert a signal to a higher intermediate (IF) frequency. The output of the mixer is fed to a poly-phase filter. The output of the poly-phase filter is fed to a programmable gain amplifier (PGA), whose output is fed to an analog-to-digital converter (ADC) to produce an output GPS signal. A saturation bit of the ADC is used to control the PGA through a digital amplifier gain control (AGC) circuit.

Abstract: The present invention discloses a mixer comprising with an input stage (100) for receiving and amplifying input signals (VINP, VINN) and an output stage (300) for outputting output signals (Voutp, Voutn). A switching stage (200) is coupled between the input stage (100) and the output stage (300), the switching stage (200) mixing the amplified input signals with a local oscillator signal (vlop, vlon) to produce the output signals (Voutp, Voutn) at the output stage (300). An RC circuit (cop, rop; con, ron) is connected to the output stage (300) and adapted to move the pole of the output signals.

Abstract: The present invention discloses a calibration circuit for a voltage-controlled oscillator (10a-10c) and also a method for calibrating the voltage-controlled oscillator. The apparatus comprises a first counter (210) for counting the number of cycles of a reference signal (Fclk) and a second counter (220) for counting the number of cycles of a feedback signal (Fin) produced by the voltage-controlled oscillator (10a-10c). The second counter (220) is further adapted to produce a difference value (OUTVAL) representative of the difference between the phase of the reference signal (Fclk) and the phase of the feedback signal (Fin). A memory (240) has a plurality of memory locations storing the difference values (OUTVAL) and capacitor selections. The apparatus further comprises a capacitor bank (90) selectable by the capacitor selections in the memory (240) and connected to the voltage-controlled oscillator (10a-10c).

Abstract: The invention teaches an amplifier (100) with an input signal (IN) coupled to the gate of a second transistor (Q2) and an output signal (OUT) coupled to an output node between a third resistor (R3) and the drain of the second transistor (Q2). A third transistor (Q3) is coupled in parallel between the output node and the gate of a second transistor (Q2). A first bias signal (Vbias) is coupled to the output node and the gate of the third transistor (Q3). The amplifier preferably also includes a plurality of switchable resistors coupled to the output node to adjust the output for process variations. The invention also describes a method of compensating for process variations in an output of an amplifier which comprises producing a reference signal dependent on the difference between a reference value and an actual value and switching one or more resistors into the output of the amplifier to adjust the output of the amplifier to reflect the process variations.

Abstract: The present invention discloses an automatic gain controller with an amplifier (10) having an amplifier output connected to a mixer (20) and a receiver signal strength indicator (100) connected to the amplifier output and to a first counter (60). The first counter (60) is adapted to produce a signal to control gain of the amplifier (10) and receives its input from the receiver signal strength indicator (100) which causes the first counter (60) to count up or down depending on the strength of the signal output from the amplifier (10). The automatic gain controller also includes a second counter (70) which is connected to an applications circuit and is adapted to produce a signal to control gain of the mixer (20). The second counter (70) receives its input from a gain control signal from the applications circuit (50) and also from the first counter (60).

Abstract: A charge transfer from signal voltage (U.sub.S) to integrating capacitance (C.sub.O) is accomplished by means of charge transfer capacitance (C.sub.i), an active element (T) and controllable switches (S.sub.61, S.sub.62, S.sub.63, S.sub.64). The operation of the circuit is additionally based on the fact that the charge transfer to the charge transfer capacitance (C.sub.i) is terminated when the transistor (T) is in a current-carrying state and that current flow is ensured by a constant-current element set. These features are combined preferably in such a way that the breaking current of charge transfer is equally great as previously said current of the constant-current element.