Patents by Inventor Ricardo E. Gonzalez
Ricardo E. Gonzalez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10089126Abstract: Function exits are instrumented in tail-call optimized code in which calls to target functions and return instructions are replaced by jump instructions. A probe engine identifies a tail-call jump and instruments the jumps to raise an exception. In response to an exception raised at the tail-call jump, an exception handler loads various registers and transferring control to a trampoline, which calls the jump target. After the target function returns, an exit probe is fired when the trampoline itself returns.Type: GrantFiled: March 21, 2013Date of Patent: October 2, 2018Assignee: VMware, Inc.Inventors: Radu Rugina, Ricardo E. Gonzalez, Zheng He, Alok Kataria
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Patent number: 9678816Abstract: Probes are employed to inject errors into code. In response to a function-entry trigger event, a probe writes a predefined test value to a return value register. The probe then cause function execution to be skipped such that the test value is returned in lieu of the value which would otherwise be returned by the function. Behavior after the error is injected may then be observed, data collected, etc. such that undesired behavior (e.g., crashes) can be identified and/or corrected. In an alternative embodiment, the probe which is triggered may write a test value to a given memory address.Type: GrantFiled: March 21, 2013Date of Patent: June 13, 2017Assignee: VMware, Inc.Inventors: Radu Rugina, Vivek Mohan Thampi, Ricardo E. Gonzalez, Alok Kataria
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Patent number: 9582278Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.Type: GrantFiled: October 9, 2008Date of Patent: February 28, 2017Assignee: Cadence Design Systems, Inc.Inventors: Albert Ren-Rui Wang, Richard Ruddell, David William Goodwin, Earl A. Killian, Nupur Bhattacharyya, Marines Puig Medina, Walter David Lichtenstein, Pavlos Konas, Rangarajan Srinivasan, Christopher Mark Songer, Akilesh Parameswar, Dror E. Maydan, Ricardo E. Gonzalez
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Patent number: 9146758Abstract: Probes are instrumented in multiple software modules of a computer system having virtual machines running therein and executed in a coordinated manner. An output of one probe may be used to conditionally trigger another probe so that the precision of collected data may be improved. In addition, outputs of probes that are triggered in different software modules by related events may be synchronized and analyzed collectively. Probes also may be parallel processed in different processors so that multiple probes can be processed concurrently.Type: GrantFiled: June 29, 2012Date of Patent: September 29, 2015Assignee: VMware, Inc.Inventors: Radu Rugina, Ricardo E. Gonzalez, Alok Kataria, Doug Covelli, Robert Benson, Matthias Hausner
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Patent number: 8924898Abstract: An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.Type: GrantFiled: June 9, 2008Date of Patent: December 30, 2014Assignee: Cadence Design Systems, Inc.Inventors: Earl A. Killian, Ricardo E. Gonzalez, Ashish B. Dixit, Monica Lam, Walter D. Lichtenstein, Christopher Rowen, John C. Ruttenberg, Robert P. Wilson, Albert Ren-Rui Wang, Dror Eliezer Maydan
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Patent number: 8875068Abstract: An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.Type: GrantFiled: June 9, 2008Date of Patent: October 28, 2014Assignee: Cadence Design Systems, Inc.Inventors: Earl A. Killian, Ricardo E. Gonzalez, Ashish B. Dixit, Monica Lam, Walter D. Lichtenstein, Christopher Rowen, John C. Ruttenberg, Robert P. Wilson, Albert Ren-Rui Wang, Dror Eliezer Maydan
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Publication number: 20140289564Abstract: Probes are employed to inject errors into code. In response to a function-entry trigger event, a probe writes a predefined test value to a return value register. The probe then cause function execution to be skipped such that the test value is returned in lieu of the value which would otherwise be returned by the function. Behavior after the error is injected may then be observed, data collected, etc. such that undesired behavior (e.g., crashes) can be identified and/or corrected. In an alternative embodiment, the probe which is triggered may write a test value to a given memory address.Type: ApplicationFiled: March 21, 2013Publication date: September 25, 2014Applicant: VMware, Inc.Inventors: Radu RUGINA, Vivek Mohan THAMPI, Ricardo E. GONZALEZ, Alok KATARIA
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Publication number: 20140289726Abstract: Function exits are instrumented in tail-call optimized code in which calls to target functions and return instructions are replaced by jump instructions. A probe engine identifies a tail-call jump and instruments the jumps to raise an exception. In response to an exception raised at the tail-call jump, an exception handler loads various registers and transferring control to a trampoline, which calls the jump target. After the target function returns, an exit probe is fired when the trampoline itself returns.Type: ApplicationFiled: March 21, 2013Publication date: September 25, 2014Applicant: VMware, Inc.Inventors: Radu Rugina, Ricardo E. Gonzalez, Zheng He, Alok Kataria
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Publication number: 20140007090Abstract: Probes are instrumented in multiple software modules of a computer system having virtual machines running therein and executed in a coordinated manner. An output of one probe may be used to conditionally trigger another probe so that the precision of collected data may be improved. In addition, outputs of probes that are triggered in different software modules by related events may be synchronized and analyzed collectively. Probes also may be parallel processed in different processors so that multiple probes can be processed concurrently.Type: ApplicationFiled: June 29, 2012Publication date: January 2, 2014Applicant: VMware, Inc.Inventors: Radu RUGINA, Ricardo E. Gonzalez, Alok Kataria, Doug Covelli, Robert Benson, Matthias Hausner
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Patent number: 8161432Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.Type: GrantFiled: October 9, 2008Date of Patent: April 17, 2012Assignee: Tensilica, Inc.Inventors: Albert Ren-Rui Wang, Richard Ruddell, David William Goodwin, Earl A. Killian, Nupur Bhattacharyya, Marines Puig Medina, Walter David Lichtenstein, Pavlos Konas, Rangarajan Srinivasan, Christopher Mark Songer, Akilesh Parameswar, Dror E. Maydan, Ricardo E. Gonzalez
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Automated processor generation system for designing a configurable processor and method for the same
Patent number: 8006204Abstract: An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.Type: GrantFiled: March 27, 2006Date of Patent: August 23, 2011Assignee: Tensilica, Inc.Inventors: Earl A. Killian, Ricardo E. Gonzalez, Ashish B. Dixit, Monica Lam, Walter D. Lichtenstein, Christopher Rowen, John C. Ruttenberg, Robert P. Wilson, Albert Ren-Rui Wang, Dror Eliezer Maydan -
Patent number: 8001266Abstract: A source processing node communicates with a destination processing node though a channel that has bandwidth requirements and is uni-directional. The source processing node generates the channel to the destination processing node. The destination processing node then accepts the channel. The source processing node allocates a transmit buffer for the channel. The destination processing node also allocates a receive buffer for the channel. A source processing element writes data to the transmit buffer for the channel. A source network interface transmits the data from the transmit buffer of the source processing node over the channel. A destination network interface receives the data into the receive buffer for the channel. A destination processing element receives the data from the receive buffer.Type: GrantFiled: March 31, 2004Date of Patent: August 16, 2011Assignee: Stretch, Inc.Inventors: Ricardo E. Gonzalez, Richard L. Rudell, Abhijit Ghosh, Albert R. Wang
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Patent number: 7937559Abstract: A processor generation system includes the ability to describe processors with three instruction sizes. In one example implementation, instructions can be 16-, 24- and 64-bits. This enables a new range of architectures that can exploit parallelism in architectures. In particular, this enables the generation of VLIW architectures. According to another aspect, the processor generator allows a designer to add a configurable number of load/store units to the processor. In order to accommodate multiple load/store units, local memories connected to the processor can have multiple read and write ports (one for each load/store unit). This further allows the local memories to be connected in any arbitrary connection topology. Connection box hardware is automatically generated that provides an interface between the load/store units and the local memories based on the configuration.Type: GrantFiled: June 11, 2007Date of Patent: May 3, 2011Assignee: Tensilica, Inc.Inventors: Akilesh Parameswar, James Alexander Stuart Fiske, Ricardo E. Gonzalez
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Patent number: 7613900Abstract: An integrated circuit with selectable input/output includes a first processor configured to execute instructions, an input/output interface configured to receive and transmit standard input/output communications, an inter-processor interface configured to process interprocessor communications with a second processor, and selection circuitry coupled to both the input/output interface and the inter-processor interface and configured to select between the input/output interface and the inter-processor interface.Type: GrantFiled: December 21, 2004Date of Patent: November 3, 2009Assignee: Stretch, Inc.Inventors: Ricardo E. Gonzalez, Albert R. Wang
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Patent number: 7581081Abstract: A system for processing applications includes processor nodes and links interconnecting the processor nodes. Each node includes a processing element, a software extensible device, and a communication interface. The processing element executes at least one of the applications. The software extensible device provides additional instructions to a set of standard instructions for the processing element. The communication interface communicates with other processor nodes.Type: GrantFiled: December 31, 2003Date of Patent: August 25, 2009Assignee: Stretch, Inc.Inventors: Ricardo E. Gonzalez, Albert R. Wang, Gareld Howard Banta
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Publication number: 20090177876Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.Type: ApplicationFiled: October 9, 2008Publication date: July 9, 2009Inventors: Albert Ren-Rui WANG, Richard Ruddell, David William Goodwin, Earl A. Killian, Nupur Bhattacharyya, Marines Puig Medina, Walter David Lichtenstein, Pavlos Konas, Rangarajan Srinivasan, Christopher Mark Songer, Akilesh Parameswar, Dror E. Maydan, Ricardo E. Gonzalez
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Publication number: 20090172630Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.Type: ApplicationFiled: October 9, 2008Publication date: July 2, 2009Inventors: Albert Ren-Rui Wang, Richard Ruddell, David William Goodwin, Earl A. Killian, Nupur Bhattacharyya, Marines Puig Medina, Walter David Lichtenstein, Pavlos Konas, Rangarajan Srinivasan, Christopher Mark Songer, Akilesh Parameswar, Dror E. Maydan, Ricardo E. Gonzalez
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Publication number: 20090125866Abstract: A method for decomposing a target pattern containing features to be printed on a wafer into multiple patterns. The method includes the steps of segmenting the target pattern into a plurality of patches; identifying critical features within each patch which violate minimum spacing requirements; generating a critical group graph for each of the plurality of patches having critical features, where the critical group graph of a given patch defines a coloring scheme of the critical features within the given patch, and the critical group graph identifies critical features extending into adjacent patches to the given patch; generating a global critical group graph for the target pattern, where the global critical group graph includes the critical group graphs of each of the plurality of patches, and an identification of the features extending into adjacent patches; and coloring the target pattern based on the coloring scheme defined by the global critical group graph.Type: ApplicationFiled: November 13, 2008Publication date: May 14, 2009Inventors: ALBERT REN-RUI WANG, RICHARD RUDDELL, DAVID WILLIAM GOODWIN, EARL A. KILLIAM, NUPUR BHATTACHARYYA, MARINES PUIG MEDINA, WALTER DAVID LICHTENSTEIN, PAVLOS KONAS, RANGARAJAN SRINIVASAN, CHRISTOPHER MARK SONGER, AKILESH PARAMESWAR, DROR E. MAYDAN, RICARDO E. GONZALEZ
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Patent number: 7437700Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.Type: GrantFiled: November 16, 2005Date of Patent: October 14, 2008Assignee: Tensilica, Inc.Inventors: Albert Ren-Rui Wang, Richard Ruddell, David William Goodwin, Earl A. Killian, Nupur Bhattacharyya, Marines Puig Medina, Walter David Lichtenstein, Pavlos Konas, Rangarajan Srinivasan, Christopher Mark Songer, Akilesh Parameswar, Dror E. Maydan, Ricardo E. Gonzalez
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Publication number: 20080244471Abstract: An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.Type: ApplicationFiled: June 9, 2008Publication date: October 2, 2008Inventors: Earl A. Killian, Ricardo E. Gonzalez, Ashish B. Dixit, Monica Lam, Walter D. Lichtenstein, Christopher Rowen, John C. Ruttenberg, Robert P. Wilson, Albert Ren-Rui Wang, Dror Eliezer Maydan