Patents by Inventor Ricardo E. Suarez-Gartner

Ricardo E. Suarez-Gartner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for reducing warpage of an assembly substrate
    Patent number: 5751556
    Abstract: A method and apparatus for reducing warpage of an assembly substrate and providing registration between a surface mount technology (SMT) component and the assembly substrate. The SMT component includes mounting pins extending from the component and capable of engaging corresponding apertures in the assembly substrate. Each mounting pin is registrable with a corresponding aperture in the assembly substrate. The mounting pins are capable of providing an interference fit between the SMT component and the assembly substrate.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: May 12, 1998
    Assignee: Intel Corporation
    Inventors: Peter O. Butler, Ricardo E. Suarez-Gartner