Abstract: The method and system for reprogramming instructions for a switch includes programming a redirection memory to associate a routing parameter set in a routing memory for the switch with a first line card. The routing parameter set includes a plurality of routing parameters to be provided to the switch to service the first line card. In response to an event initiating activation of a second line card in place of the first line card, the redirection memory is reprogrammed to associate the routing parameters set in the routing memory with the second line card.

Abstract: An asynchronous transfer mode (ATM) switch includes a switch memory having a plurality of discrete queues. A queue is dedicated to a connection in which a traffic stream is transmitted in cells and an inverse multiplex ATM (IMA) format. A switch controller is operable to receive a plurality of cells, to identify cells for the connection, to queue cells for the connection in the queue based on order information received with the cells, to reconstitute from the queue the traffic stream, and to switch the traffic stream and the ATM cells.

Abstract: A method, system, and logic for switching data streams are disclosed. Synchronous transport signal streams are generated. A destination for each synchronous transport signal stream is recorded in the overhead of the synchronous transport signal stream. The synchronous transport signal streams are transmitted to a switch, which routes the synchronous transport signal stream according to the recorded destination.

Abstract: A method and system for transmitting traffic having disparate rate components includes receiving a plurality of traffic streams. Each traffic stream includes a first component and a reduced rate second component associated with the first component. The first components of the traffic streams are segmented into successive cells. The second components of the traffic streams are distributed between a defined set of the cells for in-band transmission of the second components.

Abstract: A TDM switch is configured to route TDM traffic from two receive circuits to a destination. One copy of the traffic is discarded, and a memory selectively stores the other copy for routing to the TDM switch. Receive circuits contemplate both virtual tributary (VT) level and card or circuit level metrics for qualification of signals.

Abstract: The method and system for reprogramming instructions for a switch includes programming a redirection memory to associate a routing parameter set in a routing memory for the switch with a first line card. The routing parameter set includes a plurality of routing parameters to be provided to the switch to service the first line card. In response to an event initiating activation of a second line card in place of the first line card, the redirection memory is reprogrammed to associate the routing parameters set in the routing memory with the second line card.

Abstract: A time slot interchanger (TSI) for a telecommunications node includes an exchange memory and a controller. The exchange memory includes a plurality of exchange memory slots. Each exchange memory slot is sized to store a traffic channel and includes a plurality of discretely addressable fields sized to store a sub-channel. The controller is operable in response to predefined switching instructions to write a sub-channel received in a first traffic channel to a first field in a memory slot and to write a sub-channel received in a second traffic channel to a second field in the memory slot.

Abstract: A synchronous bus for a telecommunications node includes a frame repeating at a defined interval. Each frame includes a plurality of service channels. In at least one frame, a service channel individually transports traffic for a DS-0 connection. A set of service channels in the frame together transport an asynchronous transfer mode (ATM) cell.

Abstract: A system and method for generating a common flow identifier for messages flowing in each direction of a bidirectional message flow are disclosed. A packet classifier may extract header information from a packet and transform at least a subset of the header information into a flow identifier. The transformation may produce the same flow identifier for messages flowing in each direction of a bidirectional message flow. A hash table having entries for each bidirectional message flow may include the flow identifiers. The packet classifier may be used to control communications between an internal network and external resources.

Abstract: An asynchronous transfer mode (ATM) switch includes a switch memory having a plurality of discrete queues. A queue is dedicated to a connection in which a traffic stream is transmitted in cells and an inverse multiplex ATM (IMA) format. A switch controller is operable to receive a plurality of cells, to identify cells for the connection, to queue cells for the connection in the queue based on order information received with the cells, to reconstitute from the queue the traffic stream, and to switch the traffic stream and the ATM cells.

Abstract: A synchronous switch for a telecommunications node includes a switch interface, a switch controller, and a switch memory. The switch interface is operable to terminate a bus and to receive from the bus a frame having a plurality of time slots. The time slots are each operable to transport a traffic cell. The switch controller is operable to determine a type for each traffic cell received at the switch interface and to determine based on the type for a traffic cell an address for storing the traffic cell in the switch memory. The switch memory is operable to receive the traffic cell from the switch interface and the address for storing the traffic cell from the switch controller and to store the traffic cell at the address.

Abstract: A rate adjustable backplane includes a set of switch slots configured to receive one or more switch cards forming a switch core and a plurality of line slots each configured to receive a line card. A low speed bus couples the line slots to the set of switch slots. A high speed bus also couples the line slots to the set of switch slots. Each line slot includes a low speed connector coupled to the low speed bus and a high speed connector coupled to the high speed bus. The low speed connector is adapted to receive a mating connector of a line card to establish a low speed communication connection between the line card and the switch core. The high speed connector is adapted to receive a mating connector of the line card to establish a high speed link between the line card and the switch core.

Abstract: A bus for a telecommunications node includes a frame repeating at a defined interval and including a defined number of slots. Each slot includes an overhead portion identifying a type of traffic in the slot and a service traffic portion transporting traffic of the type. A first slot in at least one frame transports in the service traffic portion asynchronous traffic and routing information for the asynchronous traffic in the telecommunications node. A second slot in the frame transports synchronous traffic in the service traffic portion and has a location in the frame associated with routing information for the synchronous traffic in the telecommunications node.

Abstract: A switch card for telecommunications node includes a shared memory operable to store traffic channels. A time slot interchanger (TSI) is coupled to a first bus and to the shared memory. The TSI is operable based on predefined switching instructions to access the shared memory to stored traffic channels received from the first bus and to retrieve traffic channels for transmission on the first bus. An asynchronous transfer mode (ATM) switch is operable to switch a traffic cell based on header information in the traffic cell. A traffic converter is operable to convert traffic channels retrieved from the shared memory to traffic cells for processing by a bus fuser and to convert traffic cells to traffic channels for storage in the shared memory. The bus fuser is coupled to the shared memory through the traffic converter, the ATM switch, and a second bus.

Abstract: An ATM layer device for interfacing between a physical layer device and an ATM switch, which includes means for prepending and postpending of switch routing information to cells destined to enter the switch and for removing such information from cells having left the switch