Patents by Inventor Riccardo Muzzetto
Riccardo Muzzetto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210065763Abstract: Methods, systems, and devices for word line timing management are described. In some examples, a digit line may be precharged as part of accessing a memory cell. The memory cell may include a storage component and a selection component. A word line may be coupled with the selection component, and the word line may be selected in order to couple the storage component with the digit line, by way of the selection component. The word line may be selected while the digit line is still being precharged, and the storage component may become coupled with the digit line with reduced delay after the end of precharging of the digit line, concurrent with the end of the precharging of the digit line, or while the digit line is still being charged. Related techniques for sensing a logic state stored by the memory cell are also described.Type: ApplicationFiled: August 27, 2019Publication date: March 4, 2021Inventors: Umberto Di Vincenzo, Ferdinando Bedeschi, Riccardo Muzzetto
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Patent number: 10916288Abstract: Methods, systems, and devices for sensing techniques for a memory cell are described to enable a latch to sense a logic state of a memory cell. A transistor coupled with a memory cell may boost a first voltage associated with the memory cell to a second voltage via one or more parasitic capacitances of the transistor. The second voltage may be developed on a first node of a sense component, and the second voltage may be shifted to a third voltage at a first node of the sense component by applying a voltage to a shift node coupled with a capacitor of the sense component. Similar boosting and shifting operations may be performed to develop a reference voltage on a second node of the sense component. The sense component may sense the state of the memory cell by comparing with the reference voltage.Type: GrantFiled: July 18, 2019Date of Patent: February 9, 2021Assignee: Micron Technology, Inc.Inventors: Umberto Di Vincenzo, Efrem Bolandrina, Riccardo Muzzetto, Ferdinando Bedeschi
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Patent number: 10910054Abstract: The present provision includes apparatuses, methods, and systems for charge separation for memory sensing. An embodiment includes applying a sensing voltage to a memory cell, and determining a data state of the memory cell based, at least in part, on a comparison of an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell before a particular reference time and an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time.Type: GrantFiled: September 3, 2019Date of Patent: February 2, 2021Assignee: Micron Technology, Inc.Inventors: Umberto Di Vincenzo, Riccardo Muzzetto, Ferdinando Bedeschi
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Publication number: 20210020221Abstract: Methods, systems, and devices for sensing techniques for a memory cell are described to enable a latch to sense a logic state of a memory cell. A transistor coupled with a memory cell may boost a first voltage associated with the memory cell to a second voltage via one or more parasitic capacitances of the transistor. The second voltage may be developed on a first node of a sense component, and the second voltage may be shifted to a third voltage at a first node of the sense component by applying a voltage to a shift node coupled with a capacitor of the sense component. Similar boosting and shifting operations may be performed to develop a reference voltage on a second node of the sense component. The sense component may sense the state of the memory cell by comparing with the reference voltage.Type: ApplicationFiled: July 18, 2019Publication date: January 21, 2021Inventors: Umberto Di Vincenzo, Efrem Bolandrina, Riccardo Muzzetto, Ferdinando Bedeschi
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Patent number: 10861529Abstract: Methods, systems, and apparatuses for self-referencing sensing schemes are described. A cell having two transistors, or other switching components, and one capacitor, such as a ferroelectric capacitor, may be sensed using a reference value that is specific to the cell. The cell may be read and sampled via one access line, and the cell may be used to generate a reference voltage and sampled via another access line. For instance, a first access line of a cell may be connected to one read voltage while a second access line of the cell is isolated from a voltage source; then the second access line may be connected to another read voltage while the first access line is isolate from a voltage source. The resulting voltages on the respective access lines may be compared to each other and a logic value of the cell determined from the comparison.Type: GrantFiled: April 17, 2019Date of Patent: December 8, 2020Assignee: Micron Technology, Inc.Inventor: Riccardo Muzzetto
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Publication number: 20200321053Abstract: Methods, systems, devices, and techniques for read operations are described. In some examples, a memory device may include a first transistor (e.g., memory node transistor) configured to receive a precharge voltage at a first gate and output first voltage based on a threshold of the first transistor to a reference node via a first switch. The device may include a second transistor (e.g., a reference node transistor) configured to receive a precharge voltage and output a second voltage based on a threshold of the second transistor to a memory node via a second switch. The first voltage may be modified by a reference voltage and input to the second transistor. The second voltage may be modified by a voltage stored on a memory cell and input to the first transistor. The first and second transistor may output third and fourth voltages to be sampled to a latch.Type: ApplicationFiled: June 18, 2020Publication date: October 8, 2020Inventors: Ferdinando Bedeschi, Riccardo Muzzetto, Umberto Di Vincenzo
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Patent number: 10726917Abstract: Methods, systems, devices, and techniques for read operations are described. In some examples, a memory device may include a first transistor (e.g., memory node transistor) configured to receive a precharge voltage at a first gate and output first voltage based on a threshold of the first transistor to a reference node via a first switch. The device may include a second transistor (e.g., a reference node transistor) configured to receive a precharge voltage and output a second voltage based on a threshold of the second transistor to a memory node via a second switch. The first voltage may be modified by a reference voltage and input to the second transistor. The second voltage may be modified by a voltage stored on a memory cell and input to the first transistor. The first and second transistor may output third and fourth voltages to be sampled to a latch.Type: GrantFiled: January 23, 2019Date of Patent: July 28, 2020Assignee: Micron Technology, Inc.Inventors: Ferdinando Bedeschi, Riccardo Muzzetto, Umberto Di Vincenzo
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Publication number: 20200234761Abstract: Methods, systems, devices, and techniques for read operations are described. In some examples, a memory device may include a first transistor (e.g., memory node transistor) configured to receive a precharge voltage at a first gate and output first voltage based on a threshold of the first transistor to a reference node via a first switch. The device may include a second transistor (e.g., a reference node transistor) configured to receive a precharge voltage and output a second voltage based on a threshold of the second transistor to a memory node via a second switch. The first voltage may be modified by a reference voltage and input to the second transistor. The second voltage may be modified by a voltage stored on a memory cell and input to the first transistor. The first and second transistor may output third and fourth voltages to be sampled to a latch.Type: ApplicationFiled: January 23, 2019Publication date: July 23, 2020Inventors: Ferdinando Bedeschi, Riccardo Muzzetto, Umberto Di Vincenzo
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Publication number: 20200211614Abstract: Methods, systems, and devices for a source follower-based sensing architecture and sensing scheme are described. In one example, a memory device may include a sense circuit that includes two source followers that are coupled to each other and to a sense amplifier. A method of operating the memory device may include transferring a digit line voltage to one of the source followers and transferring a reference voltage to the other source follower. After transferring the digit line voltage and the reference voltage, the source followers may be enabled so that signals representative of the digit line voltage and the reference voltage are transferred from the outputs of the source followers to the sense amplifier for sensing.Type: ApplicationFiled: March 9, 2020Publication date: July 2, 2020Inventors: Hyun Yoo Lee, Suryanarayana B. Tatapudi, Huy T. Vo, Ferdinando Bedeschi, Umberto Di Vincenzo, Riccardo Muzzetto
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Patent number: 10636470Abstract: Methods, systems, and devices for a source follower-based sensing architecture and sensing scheme are described. In one example, a memory device may include a sense circuit that includes two source followers that are coupled to each other and to a sense amplifier. A method of operating the memory device may include transferring a digit line voltage to one of the source followers and transferring a reference voltage to the other source follower. After transferring the digit line voltage and the reference voltage, the source followers may be enabled so that signals representative of the digit line voltage and the reference voltage are transferred from the outputs of the source followers to the sense amplifier for sensing.Type: GrantFiled: September 4, 2018Date of Patent: April 28, 2020Assignee: Micron Technology, Inc.Inventors: Hyun Yoo Lee, Suryanarayana B. Tatapudi, Huy T. Vo, Ferdinando Bedeschi, Umberto Di Vincenzo, Riccardo Muzzetto
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Publication number: 20200075076Abstract: Methods, systems, and devices for a source follower-based sensing architecture and sensing scheme are described. In one example, a memory device may include a sense circuit that includes two source followers that are coupled to each other and to a sense amplifier. A method of operating the memory device may include transferring a digit line voltage to one of the source followers and transferring a reference voltage to the other source follower. After transferring the digit line voltage and the reference voltage, the source followers may be enabled so that signals representative of the digit line voltage and the reference voltage are transferred from the outputs of the source followers to the sense amplifier for sensing.Type: ApplicationFiled: September 4, 2018Publication date: March 5, 2020Inventors: Hyun Yoo Lee, Suryanarayana B. Tatapudi, Huy T. Vo, Ferdinando Bedeschi, Umberto Di Vincenzo, Riccardo Muzzetto
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Publication number: 20200051606Abstract: Methods and devices for reading a memory cell using a sense amplifier with split capacitors is described. The sense amplifier may include a first capacitor and a second capacitor that may be configured to provide a larger capacitance during certain portions of a read operation and a lower capacitance during other portions of the read operation. In some cases, the first capacitor and the second capacitor are configured to be coupled in parallel between a signal node and a voltage source during a first portion of the read operation to provide a higher capacitance. The first capacitor may be decoupled from the second capacitor during a second portion of the read operation to provide a lower capacitance during the second portion.Type: ApplicationFiled: August 19, 2019Publication date: February 13, 2020Inventors: Umberto Di Vincenzo, Ferdinando Bedeschi, Riccardo Muzzetto
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Publication number: 20200005868Abstract: The present disclosure includes apparatuses, methods, and systems for charge separation for memory sensing. An embodiment includes applying a sensing voltage to a memory cell, and determining a data state of the memory cell based, at least in part, on a comparison of an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell before a particular reference time and an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time.Type: ApplicationFiled: September 3, 2019Publication date: January 2, 2020Inventors: Umberto Di Vincenzo, Riccardo Muzzetto, Ferdinando Bedeschi
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Publication number: 20190341093Abstract: Self-referencing memory device, techniques, and methods are described herein. A self-referencing memory device may include a ferroelectric memory cell. The self-referencing memory device may be configured to determine a logic state stored in a memory cell based on a state signal generated using the ferroelectric memory cell and a reference signal generated using the ferroelectric memory cell. The biasing of the plate line of the ferroelectric memory cell may be used to generate the voltage need to generate the state signal during a first time period of an access operation and to generate the reference signal during a second time period of the access operation. Procedures and operations related to a self-referencing memory device are described.Type: ApplicationFiled: July 10, 2019Publication date: November 7, 2019Inventor: Riccardo Muzzetto
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Patent number: 10446232Abstract: The present provision includes apparatuses, methods, and systems for charge separation for memory sensing. An embodiment includes applying a sensing voltage to a memory cell, and determining a data state of the memory cell based, at least in part, on a comparison of an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell before a particular reference time and an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time.Type: GrantFiled: December 19, 2017Date of Patent: October 15, 2019Assignee: Micron Technology, Inc.Inventors: Umberto Di Vincenzo, Riccardo Muzzetto, Ferdinando Bedeschi
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Patent number: 10446214Abstract: Methods and devices for reading a memory cell using a sense amplifier with split capacitors is described. The sense amplifier may include a first capacitor and a second capacitor that may be configured to provide a larger capacitance during certain portions of a read operation and a lower capacitance during other portions of the read operation. In some cases, the first capacitor and the second capacitor are configured to be coupled in parallel between a signal node and a voltage source during a first portion of the read operation to provide a higher capacitance. The first capacitor may be decoupled from the second capacitor during a second portion of the read operation to provide a lower capacitance during the second portion.Type: GrantFiled: August 13, 2018Date of Patent: October 15, 2019Assignee: Micron Technology, Inc.Inventors: Umberto Di Vincenzo, Ferdinando Bedeschi, Riccardo Muzzetto
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Publication number: 20190311759Abstract: Methods, systems, and apparatuses for self-referencing sensing schemes are described. A cell having two transistors, or other switching components, and one capacitor, such as a ferroelectric capacitor, may be sensed using a reference value that is specific to the cell. The cell may be read and sampled via one access line, and the cell may be used to generate a reference voltage and sampled via another access line. For instance, a first access line of a cell may be connected to one read voltage while a second access line of the cell is isolated from a voltage source; then the second access line may be connected to another read voltage while the first access line is isolate from a voltage source. The resulting voltages on the respective access lines may be compared to each other and a logic value of the cell determined from the comparison.Type: ApplicationFiled: April 17, 2019Publication date: October 10, 2019Inventor: Riccardo Muzzetto
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Patent number: 10395715Abstract: Self-referencing memory device, techniques, and methods are described herein. A self-referencing memory device may include a ferroelectric memory cell. The self-referencing memory device may be configured to determine a logic state stored in a memory cell based on a state signal generated using the ferroelectric memory cell and a reference signal generated using the ferroelectric memory cell. The biasing of the plate line of the ferroelectric memory cell may be used to generate the voltage need to generate the state signal during a first time period of an access operation and to generate the reference signal during a second time period of the access operation. Procedures and operations related to a self-referencing memory device are described.Type: GrantFiled: August 25, 2017Date of Patent: August 27, 2019Assignee: Micron Technology, Inc.Inventor: Riccardo Muzzetto
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Publication number: 20190189211Abstract: The present disclosure includes apparatuses, methods, and systems for charge separation for memory sensing. An embodiment includes applying a sensing voltage to a memory cell, and determining a data state of the memory cell based, at least in part, on a comparison of an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell before a particular reference time and an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time.Type: ApplicationFiled: December 19, 2017Publication date: June 20, 2019Inventors: Umberto Di Vincenzo, Riccardo Muzzetto, Ferdinando Bedeschi
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Patent number: 10304514Abstract: Methods, systems, and apparatuses for self-referencing sensing schemes are described. A cell having two transistors, or other switching components, and one capacitor, such as a ferroelectric capacitor, may be sensed using a reference value that is specific to the cell. The cell may be read and sampled via one access line, and the cell may be used to generate a reference voltage and sampled via another access line. For instance, a first access line of a cell may be connected to one read voltage while a second access line of the cell is isolated from a voltage source; then the second access line may be connected to another read voltage while the first access line is isolate from a voltage source. The resulting voltages on the respective access lines may be compared to each other and a logic value of the cell determined from the comparison.Type: GrantFiled: July 5, 2017Date of Patent: May 28, 2019Assignee: Micron Technology, Inc.Inventor: Riccardo Muzzetto