Abstract: Methods and systems for operating a double-base bidirectional power bipolar transistor. Two timing phases are used to transition into turn-off: one where each base is shorted to its nearest emitter/collector region, and a second one where negative drive is applied to the emitter-side base to reduce the minority carrier population in the bulk substrate. A diode prevents reverse turn-on while negative base drive is being applied.

Abstract: An LED module is disclosed containing an integrated MOSFET driver transistor in series with an LED. In one embodiment, GaN-based LED layers are epitaxially grown over an interface layer on a silicon substrate. The MOSFET gate is formed in a trench in the silicon substrate and creates a vertical channel between a top source and a bottom drain when the gate is biased to turn on the LED. A conductor on the die connects the MOSFET in series with the LED. One power electrode is located on a top of the die, another power electrode is located on the bottom of the die, and the gate electrode may be on the top or the side of the die.

Abstract: In one embodiment, a RESURF structure between a source and a drain in a lateral MOSFET is formed in a trench having a flat bottom surface and angled sidewalls toward the source. Alternating P and N-type layers are epitaxially grown in the trench, and their charges balanced to achieve a high breakdown voltage. In the area of the source, the ends of the P and N-layers angle upward to the surface under the lateral gate and contact the body region. Thus, for an N-channel MOSFET, a positive gate voltage above the threshold forms a channel between the source and the N-layers in the RESURF structure as well as creates an inversion of the ends of the P-layers near the surface for low on-resistance. In another embodiment, the RESURF structure is vertically corrugated by being formed around trenches, thus extending the length of the RESURF structure for a higher breakdown voltage.

Abstract: A high power vertical insulated-gate switch is described that includes an active region, containing a cell array, and a surrounding termination region. The termination region is for at least the purpose of controlling a breakdown voltage and does not contain any switching cells. Assuming the anode is the silicon substrate (p-type), it is desirable to have good hole injection efficiency from the substrate in the active region in the device's on-state. Therefore, the substrate should be highly doped (p++) in the active region. It is desirable to have poor hole injection efficiency in the termination region so that there is a minimum concentration of holes in the termination region when the switch is turned off. Various doping techniques are disclosed that cause the substrate to efficiency inject holes into the active region but inefficiently inject holes into the termination region during the on-state.

Abstract: Methods of expressing animation in a data stream are disclosed. In one embodiment, a method of expressing animation in a data stream includes defining animation states in the data stream with each state having at least one property such that properties are animated as a group. The animation states that are defined in the data stream may be expressed as an extension of a styling sheet language. The data stream may include web content and the defined animation states.

Abstract: An exemplary printable composition of a liquid or gel suspension of diodes generally includes a plurality of diodes, a first solvent and/or a viscosity modifier. An exemplary apparatus may include: a plurality of diodes; at least a trace amount of a first solvent; and a polymeric or resin film at least partially surrounding each diode of the plurality of diodes. Various exemplary diodes have a lateral dimension between about 10 to 50 microns and about 5 to 25 microns in height. Other embodiments may also include a plurality of substantially chemically inert particles having a range of sizes between about 10 to about 50 microns.

Abstract: In one embodiment, a power MOSFET or IGBT cell includes an N-type drift region grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed over the drift region. A P-well is formed over the N-type layer, and an N+ source/emitter region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension into a trench. A positive gate voltage inverts the lateral channel and increases the vertical conduction in the N-type layer along the sidewalls of the trench to reduce on-resistance. A vertical shield field plate is also in the trench and may be connected to the gate. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage. Floating P-islands in the N-type drift region increase breakdown voltage and reduce the saturation current.

Abstract: In one embodiment, a printed security mark comprises a random arrangement of printed LEDs and a wavelength conversion layer. During fabrication of the mark, the LEDs are energized, and the resulting dot pattern is converted into a unique digital first code and stored in a database. The emitted spectrum vs. intensity and persistence of the wavelength conversion layer is also encoded in the first code. The mark may be on a credit card, casino chip, banknote, passport, etc. to be authenticated. For authenticating the mark, the LEDs are energized and the dot pattern, spectrum vs. intensity, and persistence are converted into a code and compared to the first code stored in the database. If there is a match, the mark is authenticated.

Abstract: In one embodiment, a printed LED area comprises a random arrangement of printed LEDs and a wavelength conversion layer. The LED area is embedded in an object to be authenticated, such as a credit card or a casino chip. The object may include a light guide for enabling the generated light to be emitted from any portion of the object. In one embodiment, when the LEDs are energized during authentication of the object, the existence of light emitted by the object is sufficient authentication and/or provides feedback to the user that the object is being detected. For added security, the emitted spectrum vs. intensity and persistence of the wavelength conversion layer is detected and encoded in a first code, then compared to valid codes stored in the database. If there is a match, the object is authenticated.

Abstract: Power devices using refilled trenches with permanent charge at or near their sidewalls. These trenches extend vertically into a drift region.

Abstract: Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.

Abstract: The disclosed embodiments provide a system that performs document scanning. The system includes a scanner and a computing device. To enable detection of the computing device in proximity to the scanner, the computing device may be configured to advertise a scan-receiving capability using a discovery protocol. Next, the scanner may use the discovery protocol to identify a set of computing devices in proximity to the scanner, including the computing device. The scanner may then provide the set of computing devices to a user of the scanner and obtain, from the user of the scanner, a selection of the computing device as a recipient of the scanned document. Finally, the scanner may send the scanned document to the computing device over a network connection with the computing device.

Abstract: Methods and systems for power semiconductor devices integrating multiple quasi-vertical transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.

Abstract: In one embodiment, a power MOSFET or IGBT cell includes an N-type drift region grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed over the drift region. A P-well is formed over the N-type layer, and an N+ source/emitter region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension into a trench. A positive gate voltage inverts the lateral channel and increases the vertical conduction in the N-type layer along the sidewalls of the trench to reduce on-resistance. A vertical shield field plate is also in the trench and may be connected to the gate. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage. Floating P-islands in the N-type drift region increase breakdown voltage and reduce the saturation current.

Abstract: An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a P+ layer (e.g., a substrate), an N? epi layer, a P-well, vertical insulated gates formed in the P-well, and N+ regions between at least some of the gates, so that vertical NPN and PNP transistors are formed. A source/emitter electrode is on top, and a drain/cathode electrode is on the bottom of the substrate. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gates, referenced to the source/emitter electrode. Some of the cells are passive, having gates that are either not connected to the active gates or having gates that are shorted to their associated N+ regions, to customize the input capacitance and lower the saturation current. Other techniques are described to form the passive cells.

Abstract: Methods and systems for double-sided semiconductor device fabrication. Devices having multiple leads on each surface can be fabricated using a high-temperature-resistant handle wafer and a medium-temperature-resistant handle wafer. Dopants can be introduced on both sides shortly before a single long high-temperature diffusion step diffuses all dopants to approximately equal depths on both sides. All high-temperature processing occurs with no handle wafer or with a high-temperature handle wafer attached. Once a medium-temperature handle wafer is attached, no high-temperature processing steps occur. High temperatures can be considered to be those which can result in damage to the device in the presence of aluminum-based metallizations.

Abstract: Methods and systems for operating a double-base bidirectional power bipolar transistor. Two timing phases are used to transition into turn-off: one where each base is shorted to its nearest emitter/collector region, and a second one where negative drive is applied to the emitter-side base to reduce the minority carrier population in the bulk substrate. A diode prevents reverse turn-on while negative base drive is being applied.

Abstract: An active target has a target face that is backlit by LEDs, where a detection layer behind the target face detects a new projectile hole in the target, such as from a gun or an arrow. The detection layer may be formed of one or more resistive layers, and the detected increase in resistance due to a new projectile hole being created is sensed and correlated to an XY position of the hole. The location of the new hole is transmitted via an RF signal to the shooter's portable device, such as a smartphone, and the shooter sees the location of the hit relative to the target face in real time. The LEDs may be dynamically controlled. The target is disposable and is supported by a support base containing the control electronics and transmitter.

Abstract: Power devices using refilled trenches with permanent charge at or near their sidewalls. These trenches extend vertically into a drift region.

Abstract: An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n? epi layer, a p-well, vertical insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gate, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for shorting the base of the NPN transistor to its emitter, to turn the NPN transistor off when the p-channel MOSFET is turned on by a slight negative voltage applied to the gate. This allows the IGTO device to be more easily turned off while in a latch-up condition, when the device is acting like a thyristor.