Abstract: A single-electron tunneling (SET) element used as a logic or memory element includes at least one tunneling junction with a minute metal-insulator-metal sandwich structure, and a biasing power source which is connected in series to the at least one tunneling junction and whose ON/OFF operation is controlled by an external control input. SET oscillations are generated in the at least one tunneling junction and the generated oscillations are phase-locked to subharmonics of a pump signal supplied from an AC power source, to thus exhibit a plurality of stable phase states. Also, a plurality of gates, each including the SET element, are constituted in the form of a logic network to realize a predetermined logic operation in a computer. In the logic network, an input signal with a frequency half that of the pump signal is continually applied to a specified gate among the plurality of gates, while the biasing power sources of all of the gates are kept in ON state.

Abstract: A superlattice of LT-GaAs layers and another semiconductor layers such as LT-AlGaAs or HT-GaAs is grown on a substrate. Lattice imperfectness such as strain or crystal defects is selectively introduced. Then, the superlattice is annealed to produce As precipitates at selected locations of the LT-GaAs layers. When strain is given by metal electrodes, anisotropic etching and self-alined metal deposition can be done utilizing these electrodes. Various semiconductor devices, particularly SET device can be manufactured utilizing those metallic precipitates.

Abstract: A superlattice of LT-GaAs layers and another semiconductor layers such as LT-AlGaAs or HT-GaAs is grown on a substrate. Lattice imperfectness such as strain or crystal defects is selectively introduced. Then, the superlattice is annealed to produce As precipitates at selected locations of the LT-GaAs layers. When strain is given by metal electrodes, anisotropic etching and self-alined metal deposition can be done utilizing these electrodes. Various semiconductor devices, particularly SET devices can be manufactured utilizing those metallic precipitates.

Abstract: A resonant-tunneling, heterostructure bipolar transistor having a quantum well between emitter contact and collector region is described. In one embodiment, a compositionally graded portion of the emitter region is adjacent to the base region, and there is a double barrier in the base region. In another embodiment the quantum well is defined by the emitter and a potential barrier in the base region. Further embodiments have a quantum well between emitter and collector regions or else within the emitter region.

Abstract: Complementary structure implemented in Group III-V compound semiconductors is obtained by using an n-channel field effect transistor and a p-channel MODFET.