Abstract: The present invention provides an illuminated decorative item, a decorative item made of ribbon and an illumination circuitry for a decorative item made of ribbon. The illuminated decorative item comprises a decorative body created with at least one elongated strip of material, the body having a base; a light source disposed at the base; an energy source electrically connected to the light source to supply energy to the light source; and at least one optic fiber, each optic fiber comprising an elongated body having a base end and a free end, the base end being close to and oriented towards the light source, the free end being arranged to visually complement the decorative body; wherein the energy source supplies energy to the light source, at least some light emitted by the light source enters the optic fiber at the base end, propagates inside the optic fiber, and exits from the free end thus generating an illumination at the free end and creating a illumination effect for the decorative item.

Abstract: The present invention provides an illuminated decorative item, a decorative item made of ribbon and an illumination circuitry for a decorative item made of ribbon. The illuminated decorative item comprises a decorative body created with at least one elongated strip of material, the body having a base; a light source disposed at the base; an energy source electrically connected to the light source to supply energy to the light source; and at least one optic fiber, each optic fiber comprising an elongated body having a base end and a free end, the base end being close to and oriented towards the light source, the free end being arranged to visually complement the decorative body; wherein the energy source supplies energy to the light source, at least some light emitted by the light source enters the optic fiber at the base end, propagates inside the optic fiber, and exits from the free end thus generating an illumination at the free end and creating a illumination effect for the decorative item.

Abstract: An emulator executes on a second data processing system as a second system user level process including a first system user level program, a first system executive program, and first system user and executive tasks. An emulator level is interposed between the second system user level process and a kernel level and contains pseudo device drivers. Each pseudo device driver corresponds to a first system input/output device. The kernel level includes kernel processes, each kernel process corresponding to a pseudo device driver. The second system hardware platform includes a plurality of second system input/output devices, wherein each second system input output device corresponds to a kernel process. Each combination of a pseudo device driver, a corresponding kernel process and a corresponding second system input/output device executes in a second system process and emulates the operations of a corresponding first system input/output task and the corresponding first system input/output device.

Abstract: An application such as an interpretative emulator executes a wide range of different classes of emulated program instructions developed for the processor architecture being emulated on a host system which includes an dual integer pipelined execution unit. The sets of RISC instructions which execute emulated program instructions are organized within the emulator so as to be processed as two distinct instruction streams by the dual integer pipelined execution units wherein one of the pipelined unit performs the steps necessary to completing a current or foreground like operation on each emulated program instruction while the other pipelined unit performs the steps of an anticipated lookahead or background like operation on the next emulated program instruction.

Abstract: A processing unit couples to a system bus in common with a peer processor, a main memory, in addition to other units, and includes a microprocessor which tightly couples to a local memory also accessible from such bus. The processing unit also includes an addressable electrically erasable programmable read only memory (EEPROM) unit which is coupled to the microprocessor and the system bus. The EEPROM unit stores in first and second separate regions, both of which occupy the same address space normally allocated for storing the microprocessor's boot code, on-board diagnostic (OBD) routines and operating system boot routines, respectively. EEPROM control circuits at power-up, condition the EEPROM unit to address the first region for executing OBD routines to verify that the processing unit is operating properly, including the ability to properly issue commands to units connected to the system bus.

Abstract: A bus interface priority network provides access to a system bus by a plurality of different types of requestors as a function of the types of transactions they are required to process. The network includes programmable circuit for identifying the type of requestor and selecting a delay for accessing the system bus on the basis of requestor type thereby eliminating the need to adjust timing to the slowest requestor.

Abstract: A virtual memory unit (VMU) includes a state machine for controlling its operations in response to commands received from another unit. The state machine includes a plurality of programmable array logic (PAL) devices which are connected to gather status from the different sections of the unit. The outputs of the PAL devices connect in common and supply a first address input to an addressable state memory. The state memory includes a plurality of locations, each of which stores a binary code defining a different machine state. The state memory locations are accessed as a function of the status signals and current state and used in turn to generate the required subcommands for executing the received commands. The state machine makes it possible to easily classify the received commands to their complexity and urgency in terms of their effect on overall system performance.

Abstract: A processing unit tightly couples to a system bus which utilizes a split cycle bus protocol and includes a local memory which is accessible from such bus. The local memory couples to a high speed synchronous bus which operates according to a predetermined bus protocol. The processing unit includes a state machine which couples to the high speed synchronous bus and to the asynchronous system bus. The state machine emulates the predetermined bus synchronous protocol in transferring commands issued to the local memory from the system bus which uses the split cycle protocol.

Abstract: A high performance microprocessor bus state machine couples to a synchronous local bus in common with another state machine for accessing a local memory according to a preestablished bus protocol. Circuit means cosines the state of a predetermined protocol bus signal indicating the release of the local bus and transitions of the clock signal which are not used for synchronizing the operations of the state machines. The resulting signal applies required address and control signals in advance to the local bus enabling the non-microprocessor state machine to generate the required address strobe to local memory on the next clock which follows the release of the local bus by the microprocessor which eliminates a clock cycle whenever local bus control passes from the microprocessor bus state machine to another state machine.

Abstract: A high performance microprocessor has associated therewith, protocol monitoring apparatus for monitoring all of the commands issued by the microprocessor and detecting when the protocol was not completed properly or completed within certain preestablished periods of time. When the monitor/timing circuits detect a protocol error, the monitoring apparatus operates to generate an output control signal which unwedges the microprocessor enabling it to continue further processing. Additionally, the monitoring apparatus includes a register for storing the address and command that the microprocessor was executing at the time of the protocol error. The same register is also used to capture address and command information for any other type of error.

Abstract: A memory system tightly couples to a high performance microprocessor through a synchronous bus. The logic circuits included in the memory system generate a blipper pulse signal using successive transitions of clock pulse signals other than the edges used to synchronize microprocessor and memory operations. The blipper pulse signal is logically combined with the memory's column address strobe timing signal which is derived from the synchronizing edges of clock pulse signals which defines the duration of the column address interval required for accessing of a pair of DRAM memories during successive memory cycles for providing sequences of four memory read responses with no wait state.

Abstract: A virtual memory unit (VMU) includes a state machine for controlling its operations in response to commands received from another unit. The state machine includes a plurality of programmable array logic (PAL) devices which are connected to gather status from the different sections of the unit. The outputs of the PAL devices connect in common and supply a first address input to an addressable state memory. The state memory includes a plurality of locations, each of which stores a binary code defining a different machine state. The state memory locations are accessed as a function of the status signals and current state and used in turn to generate the required subcommands for executing the received commands. The state machine makes it possible to easily classify the received commands to their complexity and urgency in terms of their effect on overall system performance.

Abstract: A data processing system includes a number of subsystems coupled in common to a system bus. The subsystems communicate with each other by sending commands to each other via the system bus. Channel numbers identify the subsystems. One subsystem includes apparatus for receiving commands requiring a priority interrupt by storing vectors in a random access memory. These vectors which are addressed by the channel number of the interrupting subsystem indicate the offset to be added to the base address of an exception vector table. The exception vector stores the starting address in a memory of the requested interrupt routine.

Abstract: The pipelined central processing system (CSS) units of a multiprocessor system are tightly coupled to connect in common to a system bus for sharing main memory and input/output controllers/devices. The CSS includes several circuit boards for the different VLSI circuit chip pipelined stages and associated control circuits in addition to the bus interface unit (BIU) circuits. Each board includes one or more unusual event (UEV) detector circuits for signaling when the behavior of a stage is abnormal. The UEV fault signals from each board are collected by the BIU board. When a UEV fault is detected, the BIU board circuits prevent any further communications with the system bus and broadcasts the UEV fault signal to the other boards causing the different pipelined stages to emulate the completion of the instructions within the pipeline thereby flushing it. It is thereafter placed in a nonpipelined mode.

Abstract: A last-in, first-out register having multiple address input ports and capable of storing a plurality of addresses. Address loading operations are over-lapped with address reading operations to speed up the rate at which addresses may be stored in and retrieved from the register. When the register is full of addresses it provides an indication which permits: the addresses already stored in the register to be read out and stored in an external memory, then additional addresses to be stored in the register, and subsequently the addresses transferred to the memory for storage to be retransferred to the buffer address register for read out.

Abstract: A priority resolver shortens the time between a requesting circuit initiating a request for access to a requested circuit that is shared with other circuits and the requesting circuit actually functioning with the requested circuit. A first portion of the priority resolver circuit is associated with the requesting circuit and makes a request for access to another portion of the priority resolver circuit associated with the requested circuit before the first portion has chosen the highest priority one of a plurality of requesting circuits that have concurrently bid for access to the requested circuit. Before the portion of the priority resolver associated with the requested circuit can respond to the access request and return an access grant signal, the first portion of the priority resolver circuit has chosen the highest priority requesting circuit. In this manner the time for accessing requested circuits is decreased.

Abstract: A memory controller in which a number of local memories are primarily dedicated to the shared use of a number of local processors of a data processing system to increase the efficiency of use of both the processors and memories. A controller is associated with each local memory to control connection of any one of the local processors to its associated local memory. A local processor can also be connected via a controller and an adapter circuit connected to the controller to a system bus to obtain access to circuits connected thereto. In addition, a system processor connected to the system bus may also be connected to any particular one of the local memories via its associated controller and adapter connected thereto to load data or programs into the local memory for use by the local processors, and to read out the results of previous processing done by the local processors.

Abstract: A memory address controller addresses two memories and selectively modifies an address before it is applied to the addressing input of one of the two memories. A bit of the address is used to indicate to the controller if the address is to be modified. The same address is applied unchanged to the addressing input of the other of the two memories by the memory address controller. In this manner the addressing range is expanded.

Abstract: A data selection matrix is disclosed which uses a plurality of programmed array logic (PAL) units having input thereto portions of binary words from a plurality of sources, the PALs being responsive to control words also input thereto to jointly select one of said sources of binary words and to select the arrangement of the portions of the binary words being input thereto from the selected source of binary words.

Abstract: A memory bank selection arrangement has a memory which is made up of smaller memories each of which has a number of banks of memory. First bits of a memory address are used by an address controller for addressing a location in a selected bank of a first of the smaller memories. The address may be incremented by the controller before being used to address a second of the smaller memories, and a carry output is generated when the first bits are incremented and there is a carry from the highest order bit thereof. The memory address also includes second bits which are input to an adder which increments the number represented by the second bits responsive to the carry out from the controller to compensate for the incrementation of said first bits. The incremented or unincremented number output from the adder is used by a selector to select a bank of the smaller memories so that they can be addressed using the incremented or unincremented first bits.