Abstract: The present invention provides a drilling assembly and method that is especially useful for a bottom hole drilling assembly for drilling a borehole through an earth formation. In one embodiment, the drilling assembly is preferably comprised of a tungsten alloy which is sufficiently plastic to be able to withstand the bending, torsional, and compressive stresses which occur in a bottom hole drilling assembly. The tungsten alloy weight section may be axially moveable with respect to an outer tubular and when mounted within the bottom hole assembly, acts to place the outer tubular in tension to provide a stiffer bottom hole assembly.

Abstract: The present invention includes a method for clock recovery in a packet network. The method includes a network which receives data packets at a destination node. Then the data packets are stored in a buffer. The data packets are read out of the buffer by using a locally generated clock. The fill level of the buffer is monitored over a first period of time. A relative maximum fill level for the buffer is identified during the first period of time. Further, the relative maximum fill level is used to control the frequency of the locally generated clock so as to control the rate at which data is read out of the buffer.

Abstract: A method for synchronizing a service clock at a destination node with a service clock at a source node is provided. The method includes receiving data packets from a source node at at least one port of the destination node. At the destination node, the method determines control values for a numerically controlled oscillator for a plurality of time periods. The method selectively uses the control values to set the frequency of a service clock at the destination node for use in receiving data packets.

Abstract: Phase locked loops (PLL) providing for conditional holdover are especially suited for use in communications networks. During a holdover condition, the timing signal is generated without use of an input reference clock signal. The PLLs may either enter or remain in a holdover condition if the demonstrated or expected quality level of the output of the PLL equals or exceeds the indicated quality level of the input reference clock signal. In this manner, the timing signal has an expected quality level equal to or greater than the quality level of the reference clock signal. Accordingly, network timing errors may be reduced to levels below those associated with using the reference clock signal.

Abstract: The present invention provides the novel Dihydrate D 2-methyl-thieno-benzodiazepine and a formulation therefor.

Abstract: A method and system for providing a user interface in a data processing system to be utilized for performing a plurality of tasks on a plurality of diverse central processing complexes, wherein processes utilized to perform the plurality of tasks are transparent to a user, and wherein the user interface utilized to perform the plurality of tasks is common across diverse central processor complexes. A library containing interface parameters for each central processing complex is established. The interface parameters include information necessary to tailor the user interface for the specific target central processing complex, as well as processes for performing selected tasks within each of the central processing complexes. The user is prompted to select a task for at least one of the diverse central processing complexes. At least one interface parameter from the library of interface parameters is selected in response to the user selecting a task for at least one of the diverse central processing complexes.

Abstract: The present invention provides a process for preparing olanzapine and intermediates therefor.

Abstract: A logic circuit for detecting when the sign and most significant error bit of the digital values defining the data vector for either the In-phase or quadrature-phase have identical logic values. As illustrated, a pair of counters is used to provide an integrator with one of the counters receiving all error indications and the other receiving "good" indications and an output is provided when one of the counters first reaches a full count condition. Thus, the integrator provides an out-of-lock condition when there is an error indicative condition for more than half of a predetermined number of counts.

Abstract: A circuit capable of vector magnitude control and phase reversal for a radio signal such as an intermediate frequency signal. The circuit includes an inverting signal path and a noninverting signal path and means for selecting between the two. Further, a variable attenuation controllable from a function control input establishes the magnitude of the output signal vector. There is also disclosed a phase shifter employing two such circuits. In the phase shifter, a radio signal vector to be shifted is applied to the inputs of the two circuits, with a 90.degree. shift between the two inputs. With proper vector magnitude and phase reversal control of the two circuits, there can be provided a preselected phase shift in any quadrant.

Abstract: Circuitry for use in an IF combiner, where main and diversity receiver path signals are combined. The circuitry generates an error signal for the purpose of controlling the phase of one of these signals by deriving a broad-band phase-modulated feedback path version of the signal. No modulation is introduced into the message channel. The feedback path version of the signal is quadrature modulated and combined with signals from the main and diversity receiver paths to generate an error signal providing maximum control loop sensitivity.

Abstract: A circuit for measuring the Differential Absolute Delay Equalization between two data signals (each signal consisting of a data stream and its associated clock) is provided. The circuit generates an equalization error signal which is a composite of error signal and a pedestal voltage. The circuit also generates a replica of the pedestal voltage by taking the algebraic summation of the output of the comparison circuit and the complement of the output of the comparison circuit. The equalization error is the difference between the error signal and the replica pedestal voltage.

Abstract: The use of a nonlinear device such as a diode inserted in series with the load impedance of a transistor amplifier stage will reduce even and odd order distortion and thus improve the overall linearity characteristics of the amplifier.

Abstract: A loop phase detector circuit in which the phase offset error arising from imperfections in the circuit parameters, inter alia, temperature and power supply voltage, is reduced to a minimum by the circuit arrangement disclosed herein. The phase comparator circuit compares the phase of the output frequency of a voltage to frequency converter with an input reference signal, and provides, in complementary form, a phase comparison error signal and the complement of a phase comparison error signal. Due to temperature and supply voltage fluctuation of the circuit, the phase comparison error signal and the complementary phase comparison error signal may not be symmetrical in amplitude and may contain offset errors not directly related to phase errors.

Abstract: A method and therapeutic compositions for inducing interferon formation in vivo. To a host is administered an interferon inducer of the formula: ##SPC1##Wherein X is a member selected from the group consisting of bromo and iodo and Y is a member selected from the group consisting of methyl and ethyl when X is bromo; or Y is a member selected from the group consisting of methyl, ethyl, n-propyl, benzyl and chloro when X is iodo.