Abstract: A system for adjusting a serial communications link includes a system under test including at least one transmitter and at least one receiver coupled together via a serial data communications link, wherein at least one of the transmitter and the receiver has at least one tunable parameter, at least one controller coupled to at least one of a transmitter and a receiver via a joint test action group JTAG interface, and logic configured to adjust the at least one tunable parameter to optimize a performance of the serial data communications link.

Abstract: A system for measuring performance of a serial communications link includes a system under test including at least one transmitter and at least one receiver coupled together via a serial data communications link, wherein at least one of the transmitter and the receiver has at least one tunable parameter, at least one controller coupled to at least one of a transmitter and a receiver via a joint test action group JTAG interface, and logic configured to perform a bit error ratio test (BERT) at a plurality of receiver phase locations over a defined time period and concluding the BERT for a particular phase location if a BERT error count is greater than 0 at the particular phase location.

Abstract: A system for adjusting a serial communications link includes a system under test including at least one transmitter and at least one receiver coupled together via a serial data communications link, wherein at least one of the transmitter and the receiver has at least one tunable parameter, at least one controller coupled to at least one of a transmitter and a receiver via a joint test action group JTAG interface, and logic configured to adjust the at least one tunable parameter to optimize a performance of the serial data communications link.

Abstract: A system for measuring performance of a serial communications link includes a system under test including at least one transmitter and at least one receiver coupled together via a serial data communications link, wherein at least one of the transmitter and the receiver has at least one tunable parameter, at least one controller coupled to at least one of a transmitter and a receiver via a joint test action group JTAG interface, and logic configured to perform a bit error ratio test (BERT) at a plurality of receiver phase locations over a defined time period and concluding the BERT for a particular phase location if a BERT error count is greater than 0 at the particular phase location.

Abstract: Eye diagrams are made for signals on each channel in a group. Outlying signals not exhibiting overlap for a sampling parameter common for all channels may be ignored and a warning given. Selected, normalized eye openings are used to discover optimum sampling parameters for each channel. Locations within each eye opening are ranked according to preference. Algorithms are used to select a single best value for a sampling parameter common to all the channels, and the corresponding best other sampling parameter is found for each channel. One algorithm disregards good choices for many channels to accommodate any remaining channel by using only a commonly agreed upon value (a jury system). Another algorithm gives weight to a choice according to the number of channels that agree on that choice (majority rule). A graphical user interface facilitates the selection, and emphasizes which sampling parameters are constrained to vary together.

Abstract: A Logic Analyzer has an intuitive and informative analog presentation of signal activity and threshold settings formed by gathering a collection of factors pertaining to the measurement to be performed, such as information about which channels are members of labeled collections. A scan of signal activity is performed for each assigned channel as its threshold is briefly swept. This produces a range of voltage that describes that signal's signal activity. For each Probe Pod these ranges are then displayed in columns as adjacent vertical segments of a voltage swing Y axis along a channels-within-a-probe-pod X axis. The Y axis is labeled with actual voltage values. Superimposed upon this analog style display is a horizontal line indicating the associated threshold for that Probe Pod. Further annotations include channel identifiers and signal activity indicators whose shapes connote recurring transitions and signals that appear to be ‘stuck’ either HIGH or LOW.

Abstract: Measurements for an eye diagram of signal of interest are placed in a data structure that is examined to locate an eye opening of interest. The eye opening of interest is normalized into figure of merit units related to the operational voltage and timing requirements of the data receiver for that signal. The locations within the normalized eye opening may be taken as center locations for trial symmetric shapes that start out small and are enlarged until they first include locations not part of the normalized eye opening. The center of a largest such shape is mapped back into the units of the original eye diagram as optimum sampling parameters for data analysis equipment that uses the receiver to sample the signal once per unit interval to discover logical value. An alternative is to repeatedly remove the ‘outer layer’ of the normalized eye opening until only one location remains.

Abstract: Measurements for an eye diagram of a signal of interest are placed in a data structure that is examined to locate an eye opening of interest. The eye opening of interest is normalized into figure of merit units related to the operational voltage and timing requirements of the data receiver for that signal. The locations within the normalized eye opening may be taken as center locations for trial symmetric shapes that start out small and are enlarged until they first include locations not part of the normalized eye opening. The center of a largest such shape is mapped back into the units of the original eye diagram as optimum sampling parameters for data analysis equipment that uses the receiver to sample the signal once per unit interval to discover logical value. An alternative is to repeatedly remove the ‘outer layer’ of the normalized eye opening until only one location remains.

Abstract: An original composite eye diagram is reformulated by deliberately re-aligning its component eye diagrams according to some appropriate standard. This ‘forced-alignment’ shifts the components in one or both of the time and voltage axes. Notice is taken of the shift(s) for each channel, and that shift data is appended to the data structures for the original components. The content of the data structure can be read in its original form, or, read and force-aligned. A force-aligned composite eye diagram created from the re-aligned components can then be displayed, investigated and evaluated with any of the existing tools that used to analyze eye diagrams, simply by instructing the process that read a component eye diagram structure to reform that component as it is being read.

Abstract: Eye diagrams are made for signals on each channel in a group thereof. Outlying signals that do not exhibit overlap for a sampling parameter that is to be common for all channels may be ignored and a warning given. Selected, normalized eye openings are used to discover optimum sampling parameters for each channel. Locations within each eye opening are ranked according to preference. Algorithms are used to select a single best value for a sampling parameter common to all the channels, and the corresponding best other sampling parameter is found for each channel. One algorithm disregards good choices for many channels to accommodate any remaining channel by using only a commonly agreed upon value (a jury system). Another algorithm gives weight to a choice according to the number of channels that agree on that choice (majority rule). A graphical user interface facilitates the selection, and emphasizes which sampling parameters are constrained to vary together.

Abstract: Measurements for an eye diagram of a signal of interest are placed in a data structure that is examined to locate an eye opening of interest. The eye opening of interest has already been, or is subsequently, normalized into figure of merit units related to the operational voltage and timing requirements of the data receiver for that signal. The locations within the normalized eye opening may be taken as center locations for trial symmetric shapes that start out small and are enlarged until they first include locations not part of the normalized eye opening. The center of a largest such shape is mapped back into the units of the original eye diagram as optimum sampling parameters for data analysis equipment that uses the receiver to sample the signal once per unit interval to discover logical value. An alternative is to repeatedly remove the ‘outer layer’ of the normalized eye opening until only one location remains.

Abstract: A sampling transition-detector sets two latches to different values when an input signal comparator referenced to the selected voltage transitions during a sample interval: at the beginning one latch receives one comparison value while at the end the other latch receives an opposite comparison value. A difference (XOR) in latched values indicates a transition through the selected voltage during the sample interval. An additional latch is set by a second input signal comparator whose reference voltage is offset slightly from the selected voltage, It also clocked at the start of the sample interval. If the two latches clocked at the start of the sample interval are different, as indicated by another XOR, then the input was between the reference voltage and its offset counterpart. The OR of the two XORs is the desired indication.

Abstract: An eye diagram analyzer equips each SUT data and clock signal input channel with individually variable delays in their respective paths. For a range of signal delay of n-many SUT clock cycles, the SUT clock signal delay might be set at about n/2. For each data channel there is specified a point in time relative to an instance of the delayed clock signal (data signal delay) and a voltage threshold. The specified combination (data signal delay, threshold and which channel) is a location on an eye diagram, although the trace may or may not ever go through that location. A counter counts the number of SUT clock cycles used as instances of the reference for the eye diagram, and another counter counts the number of times the specified combination of conditions was met (“hits”).

Abstract: An eye diagram analyzer assigns a plurality of SUT data signals to be members of a labeled group of channels. There may be a plurality of such groups. In addition to mere superposition in an (X, Y) display space of the various i-many (X, Y)-valued pixels for individual component eye diagrams associated with that group, other measured data for those pixels within a group can be merged in various different modes to produce corresponding composite eye diagram presentations. E.g., in a Normalized Signal Density Mode the number of hits at each trial measurement point is summed over all channels in the group, and then divided by the total number of clock cycles measured for the ith measurement point in that group to produce a density Di associated with the corresponding ith pixel: (Xi, Yi, Di). If Di is rendered as a color or an intensity, the resulting eye diagram includes a representation (the Di) of a normalized density of transitions at each point (Xi, Yi), relative to that group as a whole.

Abstract: The time needed to perform an eye diagram measurement is minimized by initially randomly investigating the (X, Y)i that lie on a “starting” line crossing the sample space and expected to intersect any eye diagram. This finds a location on the eye diagram. Then the eye diagram is traversed as it is discovered by investigating nearest neighbors of locations found to belong to the eye diagram. Two arrays E and L of bits are established. The bits of E represent “eligible” (X, Y)i, while those of L represent “likely” (X, Y)i. At the very start of the measurement all bits in the eligible array E are set and all those in the likely array L are cleared, except that the starting line is established by setting in L and clearing in E locations for the corresponding (X, Y)i. Thereafter, locations in L that have 1s are measured in a randomly selected order.

Abstract: A system that allows an end user to optimize the performance of a logic analyzer quickly and easily is disclosed. A visual display allowing a user to see a data valid window and relative sample positions is provided. Direct graphical manipulation of the sample position allows for quick and accurate setting of sample positions. The present invention provides a graphical user interface generally comprised of the following components: a stable and transitioning data display; bus/signal labels; sample position time scale; an information icon; a timestamp icon; a graphical representation of suggested and selected sample position; a text display of selected sample position; and a legend. The present invention sets up the logic analyzer to correctly sample data from high speed, low margin systems. It measures data signals from the device under test relative to the user's state clock and automatically suggests the sampling position offset for each channel of the analyzer.

Abstract: An eye diagram analyzer equips each SUT data and clock signal input channel with individually variable delays in their respective paths. For a range of signal delay of n-many SUT clock cycles, the SUT clock signal delay might be set at about n/2. For each data channel there is specified a point in time relative to an instance of the delayed clock signal (data signal delay) and a voltage threshold. The specified combination (data signal delay, threshold and which channel) is a location on an eye diagram, although the trace may or may not ever go through that location. A counter counts the number of SUT clock cycles used as instances of the reference for the eye diagram, and another counter counts the number of times the specified combination of conditions was met (“hits”).

Abstract: Delay induced apparent amplitude desensitization in a data signal channel and its accompanying worm-like distortion in an Eye Diagram Analyzer is avoided by altering the measurement to avoid the need for any substantial delay in the path of the data channel threshold comparison signals. In a first technique, only enough delay will be inserted in the data channels to produce the relative adjustments needed to compensate for skew between the data channels, as determined by a calibration operation, and it is these de-skewed, but otherwise un-delayed, data threshold comparison signals that are, in rapid succession, clocked into the latches whose difference registers a hit at a given (time, voltage) pair. The clock path delay is then varied from a minimal value to a sufficiently large value capable of spanning a desired the number of eye diagram cycles.

Abstract: Once an eye diagram measurement is begun and there is an eye diagram displayed, different on-screen measurement tools may be used singly, or in combination. Each measurement involves indicating with cursors and line segments regions of the eye diagram that are of interest, and a parameter or parameters associated with each measurement tool in use is reported in a (usually) separate area of the display. An Eye Limits measurement allows the specification of a point within an eye diagram, whereupon it finds and reports the eye diagram coordinates first encountered along horizontal and vertical lines extended from the selected point (i.e., “eye opening” size). The coordinates of the point itself are also reported. A Four Point Box measurement allows the construction on the eye diagram of a rectangle having sides parallel to the coordinate axes of the eye diagram.

Abstract: An eye diagram analyzer can assign a plurality of SUT data signals to be members of a labeled group of channels. There may be a plurality of such groups. The measured data for components within a group can be merged according to various different modes into a composite eye diagram presentation. When a composite eye diagram is being displayed, the operator may position a screen pointer (cursor) over some interesting part of the eye diagram, and the analyzer will display a list those channels that contributed to the displayed pixels in that part of the eye diagram, as well as other related information. The operator may also select a channel from among the group, and then have the displayed pixels for which it is responsible be displayed in a selected color or otherwise highlighted in a way that allows them to be distinguished from all others.