Patents by Inventor Richard Anthony Conti
Richard Anthony Conti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7838390Abstract: Methods of forming integrated circuit devices include forming a trench in a surface of semiconductor substrate and filling the trench with an electrically insulating region having a seam therein. The trench may be filled by depositing a sufficiently thick electrically insulating layer on sidewalls and a bottom of the trench. Curing ions are then implanted into the electrically insulating region at a sufficient energy and dose to reduce a degree of atomic order therein. The curing ions may be ones selected from a group consisting of nitrogen (N), phosphorus (P), boron (B), arsenic (As), carbon (C), argon (Ar), germanium (Ge), helium (He), neon (Ne) and xenon (Xe). These curing ions may be implanted at an energy of at least about 80 KeV and a dose of at least about 5×1014 ions/cm2. The electrically insulating region is then annealed at a sufficient temperature and for a sufficient duration to increase a degree of atomic order within the electrically insulating region.Type: GrantFiled: October 12, 2007Date of Patent: November 23, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-jung Kim, Joo-chan Kim, Jae-eon Park, Richard Anthony Conti, Zhao Lun, Johnny Widodo, William C. Wille, Biao Zuo
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Publication number: 20090098706Abstract: Methods of forming integrated circuit devices include forming a trench in a surface of semiconductor substrate and filling the trench with an electrically insulating region having a seam therein. The trench may be filled by depositing a sufficiently thick electrically insulating layer on sidewalls and a bottom of the trench. Curing ions are then implanted into the electrically insulating region at a sufficient energy and dose to reduce a degree of atomic order therein. The curing ions may be ones selected from a group consisting of nitrogen (N), phosphorus (P), boron (B), arsenic (As), carbon (C), argon (Ar), germanium (Ge), helium (He), neon (Ne) and xenon (Xe). These curing ions may be implanted at an energy of at least about 80 KeV and a dose of at least about 5×1014 ions/cm2. The electrically insulating region is then annealed at a sufficient temperature and for a sufficient duration to increase a degree of atomic order within the electrically insulating region.Type: ApplicationFiled: October 12, 2007Publication date: April 16, 2009Inventors: Jun-jung Kim, Joo-chan Kim, Jae-eon Park, Richard Anthony Conti, Zhao Lun, Johnny Widodo, William C. Wille, Biao Zuo
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Publication number: 20080233709Abstract: A method for removing a material from a trench in a semiconductor. The method includes placing the semiconductor in a vacuum chamber, admitting a reactant into the chamber at a pressure to form a film of the reactant on a surface of the material, controlling the composition and residence time of the film on the surface of the material to etch at least a portion of the material, and removing any unwanted reactant and reaction product from the chamber or the surface of the material.Type: ApplicationFiled: March 22, 2007Publication date: September 25, 2008Applicants: Infineon Technologies North America Corp., International Business MachinesInventors: Richard Anthony Conti, Armin T. Tilke, Chris Stapelmann, Michael R. Sievers
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Controlled dopant diffusion and metal contamination in thin polycide gate conductor of MOSFET device
Patent number: 6114736Abstract: A MOSFET device is formed on a P- doped semiconductor substrate with an N- well formed therein, with a pair of isolation regions formed in the N- well with a gate oxide layer formed above the N- well. An FET device is formed with source and drain regions within the N-well, and a gate electrode formed above the gate oxide layer aligned with the source and drain regions. The gate electrode comprises a stack of layers. A polysilicon layer is formed on the gate oxide layer. A tungsten nitride dopant barrier layer is formed upon the polysilicon layer having a thickness of from about 5 nm to about 20 nm, and a tungsten silicide layer is formed upon the tungsten nitride layer.Type: GrantFiled: July 12, 1999Date of Patent: September 5, 2000Assignee: International Business Machines CorporationInventors: Karanam Balasubramanyam, Stephen Bruce Brodsky, Richard Anthony Conti, Badih El-Kareh -
Patent number: 6049131Abstract: A method and the device produced by the method of selective refractory metal growth/deposition on exposed silicon, but not on the field oxide is disclosed. The method includes preconditioning a wafer in a DHF dip followed by the steps of 1) selectively depositing a refractory metal on the exposed surfaces of the silicon substrate by reacting a refractory metal halide with the exposed surfaces of said silicon substrate; 2) limiting silicon substrate consumption by reacting the refractory metal halide with a silicon containing gas; and 3) further increasing the refractory metal thickness by reacting the refractory metal halide with hydrogen. Through an adequate pretreatment and selection of the parameters of 1) temperature; 2) pressure; 3) time; 4) flow and 5) flow ratio during each of the deposition steps, this invention adequately addresses the difficulties of uneven n+ versus p+ (source/drain) growth, deep consumption/encroachment by the refractory metal into silicon regions (e.g.Type: GrantFiled: July 3, 1997Date of Patent: April 11, 2000Assignee: International Business Machines CorporationInventors: Stephen Bruce Brodsky, Richard Anthony Conti, Seshadri Subbanna
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Patent number: 5923999Abstract: A MOSFET device is formed on a P- doped semiconductor substrate with an N- well formed therein, with a pair of isolation regions formed in the N- well with a gate oxide layer formed above the N- well. An FET device is formed with source and drain regions within the N-well, and a gate electrode formed above the gate oxide layer aligned with the source and drain regions. The gate electrode comprises a stack of layers. A polysilicon layer is formed on the gate oxide layer. A tungsten nitride dopant barrier layer is formed upon the polysilicon layer having a thickness of from about 5 nm to about 20 nm, and a tungsten silicide layer is formed upon the tungsten nitride layer.Type: GrantFiled: October 29, 1996Date of Patent: July 13, 1999Assignee: International Business Machines CorporationInventors: Karanam Balasubramanyam, Stephen Bruce Brodsky, Richard Anthony Conti, Badih El-Kareh
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Patent number: 5807788Abstract: A method and the device produced by the method of selective refractory metal growth/deposition on exposed silicon, but not on the field oxide is disclosed. The method includes preconditioning a wafer in a DHF dip followed by the steps of 1) selectively depositing a refractory metal on the exposed surfaces of the silicon substrate by reacting a refractory metal halide with the exposed surfaces of said silicon substrate; 2) limiting silicon substrate consumption by reacting the refractory metal halide with a silicon containing gas; and 3) further increasing the refractory metal thickness by reacting the refractory metal halide with hydrogen. Through an adequate pretreatment and selection of the parameters of 1) temperature; 2) pressure; 3) time; 4) flow and 5) flow ratio during each of the deposition steps, this invention adequately addresses the difficulties of uneven n+ versus p+ (source/drain) growth, deep consumption/encroachment by the refractory metal into silicon regions (e.g.Type: GrantFiled: November 20, 1996Date of Patent: September 15, 1998Assignee: International Business Machines CorporationInventors: Stephen Bruce Brodsky, Richard Anthony Conti, Seshadri Subbanna
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Patent number: 5728222Abstract: An apparatus in a chemical vapor deposition (CVD) system monitors the actual wafer/substrate temperature during the deposition process. The apparatus makes possible the production of high quality aluminum oxide films with real-time wafer/substrate control. An infrared (IR) temperature monitoring device is used to control the actual wafer temperature to the process temperature setpoint. This eliminates all atmospheric temperature probing. The need for test runs and monitor wafers as well as the resources required to perform the operations is eliminated and operating cost are reduced. High quality, uniform films of aluminum oxide can be deposited on a silicon substrates with no need for additional photolithographic steps to simulate conformality that are present in a sputtered (PVD) type application. The result is a reduction in required process steps with subsequent anticipated savings in equipment, cycle time, chemicals, reduce handling, and increased yield of devices on the substrate.Type: GrantFiled: October 12, 1995Date of Patent: March 17, 1998Assignee: International Business Machines CorporationInventors: Steven George Barbee, Richard Anthony Conti, Alexander Kostenko, Narayana V. Sarma, Donald Leslie Wilson, Justin Wai-Chow Wong, Steven Paul Zuhoski
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Patent number: 5665608Abstract: A method and apparatus for monitoring and controlling reactant vapors prior to chemical vapor deposition (CVD). The reactant vapors are monitored at full concentration without sampling as they are transported to a CVD reactor. Contaminants detected cause a process controller to switch the transport path to direct reactant vapors to a system pump.Type: GrantFiled: February 10, 1995Date of Patent: September 9, 1997Assignee: International Business Machines CorporationInventors: Jonathan Daniel Chapple-Sokol, Richard Anthony Conti, James Anthony O'Neill, Narayana V. Sarma, Donald Leslie Wilson, Justin Wai-Chow Wong
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Patent number: 5648113Abstract: A process and apparatus for Al.sub.2 O.sub.3 CVD on silicon wafers using aluminum tri-isopropoxide in a high-volume production environment is presented. The conditions required to use ATI in a production environment and provide maximum utilization of ATI are first of all delivery of ATI via direct evaporation. The ATI source bottle is pumped out (bypassing substrates) until propene and isopropanol signals are reduced to 1% of process pressure before start of aluminum oxide deposition. Either IR spectroscopy or mass spectrometry can be used to provide a control signal to the microprocessor controller. Heating the supplied tetramer to 120.degree. C. for two hours assures complete conversion to trimer. The ATI is stored at 90.degree. C. to minimize decomposition during idle periods and allow recovery of trimer upon return to 120.degree. C. for two hours. During periods of demand, the ATI is held at 120.degree. C. to minimize decomposition.Type: GrantFiled: September 30, 1994Date of Patent: July 15, 1997Assignee: International Business Machines CorporationInventors: Steven George Barbee, Jonathan Daniel Chapple-Sokol, Richard Anthony Conti, Richard Hsiao, James Anthony O'Neill, Narayana V. Sarma, Donald Leslie Wilson, Justin Wai-Chow Wong, Steven Paul Zuhoski