Abstract: A scalable circuit architecture for programmable circuitry is provided. Intellectual property (IP) blocks may be integrated into a circuit design and may be formed next to programmable logic sectors on which user logic functions are implemented. IP blocks may receive configuration data from sub-system managers (SSMs) that serve as a local configuration source for the IP blocks. Configurable endpoints in the IP blocks may be represented by memory mapped addresses that may be decoded by pipeline decoders having delay elements that prevent read data collision. A reroute layer may serve as an interface between IP blocks and one or more programmable logic sectors. The reroute layer may have a higher number of connections at a logic sector interface compared to the number of connections at an IP block interface. An IP block may route clock signals having different frequencies to respective different rows or regions in the programmable logic sectors.

Abstract: An integrated circuit may have configurable storage blocks. A configurable storage block may include a memory array and a control circuit. The configurable storage block may receive a mode selection command. The control circuit may determine to operate the configurable storage block in a first mode which may provide random access to the memory array or in a second mode which may provide access to the memory array in a predefined order based on the mode selection command. Thus, the configurable storage block may implement first-in first-cut modules or last-in first-out modules and variations thereof in addition to implementing memory modules with random access.

Abstract: An integrated circuit may have circuitry that includes a storage circuit, a processing circuit, and at least one state register to implement a finite-state machine. The storage circuit may store base addresses and output data for each state of the finite-state machine. The storage circuit may further store offset values that are based on the input data to the finite-state machine and the state transition from a current state to a next state caused by the input data. The processing circuit may compute the address of the storage circuit location where the output data of the next state is stored. The computation of this address may depend on the offset value and base address of the current state. The state register may receive the address from the processing circuit, store the address, and perform the corresponding memory access operation on the storage circuit.

Abstract: A multichip package that includes a programmable interposer is provided. Multiple integrated circuits may be mounted on the interposer. Active circuitry may also be embedded in the interposer device to facilitate protocol-based communications, debugging, and other desired circuit operations. The interposer device may include programmable interconnect routing circuitry that serves primarily to provide routing for the different circuits within the multichip package. A design tool may be used to design the interposer device. The design tool may include a standard die footprint library from which standard interface templates can be selected when designing an interposer device that has to communicate various on-interposer integrated circuits. The use of standard die footprints may simplify the design of interposers by enabling a family of devices to interface with a given interposer.