Abstract: An emitter ID ambiguity reduction system includes a Mission Data File Ambiguity Resolution matrix that contains both a) the INTEL-based emitter parameters data necessary to break emitter-by-emitter ambiguities, and b) the action(s) the Electronic Warfare (EW) system is to take to collect that data. Control software is triggered via either external command or per Mission Data File information (such as that contained in the Ambiguity Resolution Matrix). The emitter ID ambiguity reduction system includes Data collection hardware and firmware and Data Analysis OFP software algorithm(s).

Abstract: An emitter ID ambiguity reduction system includes a Mission Data File Ambiguity Resolution matrix that contains both a) the INTEL-based emitter parameters data necessary to break emitter-by-emitter ambiguities, and b) the action(s) the Electronic Warfare (EW) system is to take to collect that data. Control software is triggered via either external command or per Mission Data File information (such as that contained in the Ambiguity Resolution Matrix). The emitter ID ambiguity reduction system includes Data collection hardware and firmware and Data Analysis OFP software algorithm(s).

Abstract: A system and method for adaptive spurious signal (spur) processing at a broadband RF receiver. Spur processing addresses the detection of spurs generated by the receiver when high level RF signals are present at its input. The spurs can lead to undesired false detections. Based on signal parameters of the received RF signal, the system detects a strong enough real signal that would cause a spur and prevent generation of false reports. The adaptive spur mitigation scheme uses multiple detection and report thresholds to enable false report rejection with an improved high probability of rejecting false detections, while minimizing the adverse effects on multi-tone dynamic range. The necessary detection and report thresholds are generated based on a system level behavioral model that predicts the performance of several different types of spurs as a function of signal parameters. The thresholds are tuned to match the behavior of the dominant spur.

Abstract: A digital to analog converter (DAC) method and apparatus employs a multiplying-adding DAC, eliminating digital adder circuitry. Examples are given for multiplying a 3-bit binary number by a 2-bit binary number; however, there are no limitations to the bit-widths of the numbers to be multiplied. The multiplying-adding DAC method can be scaled up or down in bit-width by feeding the DAC with partial sums and adjusting the DAC weights accordingly. An analog to digital converter (ADC) can be placed after the DAC to generate a digital output. By multiplexing preset digital data into the DAC core for return to zero (RTZ), a true zero that is the midpoint of the DAC output range is achieved. It does not return to a rail for single-ended outputs. RTZ in DAC circuits doubles the null frequency of sin(x)/x roll-off inherent in DACs and also helps reduce switching glitches in the DAC output.

Abstract: A digital to analog converter (DAC) method and apparatus employs a multiplying-adding DAC, eliminating digital adder circuitry. Examples are given for multiplying a 3-bit binary number by a 2-bit binary number; however, there are no limitations to the bit-widths of the numbers to be multiplied. The multiplying-adding DAC method can be scaled up or down in bit-width by feeding the DAC with partial sums and adjusting the DAC weights accordingly. An analog to digital converter (ADC) can be placed after the DAC to generate a digital output. By multiplexing preset digital data into the DAC core for return to zero (RTZ), a true zero that is the midpoint of the DAC output range is achieved. It does not return to a rail for single-ended outputs. RTZ in DAC circuits doubles the null frequency of sin(x)/x roll-off inherent in DACs and also helps reduce switching glitches in the DAC output.

Abstract: A phase locked loop is frequency modulated by means of a modulation signal pplied to the loop filter thereof. The circuit is designed with two time constants, one of which determines the square wave modulation response thereof and the other the loop settling time. Each of these time constants is chosen to optimize the loop modulation response and the loop settling time.

Abstract: A clamp circuit in which, so long as the input voltage ranges between preselected voltages +E and -E, the output voltage tracks the input voltage. When the input voltage goes beyond +E or -E, the output voltage is clamped to +E or -E. When, thereafter, the input voltage is changed in the opposite sense by X volts, where .vertline.X.vertline..ltoreq. 2E below its maximum value the output voltage changes by X volts.The clamping circuit utilizes a differential amplifier and circuits providing two feedback paths between the output and inverting input of the amplifier, one or the other being operable dependent on the value of input signal to provide the clamping action described above.

Abstract: A rotor mounting a sensor to be inserted into the earth is rotatably mounted within and locked to a cylindrical housing. The latter may be dropped to the earth and may come to rest in any orientation. When at rest, the rotor is unlocked and a drive mechanism rotates the rotor with respect to the housing. Gravity causes a ball in a tortuous path in the rotor to traverse the path and to drop into one of a plurality of annularly spaced recesses in the housing when the rotor reaches a desired orientation. With the ball in place in a recess, a wedge surface on the rotor wedges against a portion of the ball extending from the recess and this stops the rotor--in the desired orientation.