Abstract: Systems and techniques are described for applying a polar bias modulation having a phase component and an amplitude component to a signal amplified by a power amplifier. The power amplifier (PA) has a plurality of amplifier gain stages and is configured to amplify an input to create an amplifier output signal. The input to the power amplitude is phase modulated based upon the phase component of the polar bias modulation, but need not be amplitude modulated. Amplitude modulation is provided by logic that includes a detector configured to receive an indication of the amplifier output as a feedback signal, a control module configured to generate a control signal based upon both the feedback signal and the amplitude component of the polar bias modulation, and a bias circuit configured to adjust a bias signal associated with at least one of the plurality of amplifier gain stages in response to the control signal.

Abstract: A technique for calibrating a transceiver of a wireless communication device includes selectively coupling an output node of a transmitter of the transceiver to an input node of a receiver of the transceiver. A calibration signal is provided, from the output node of the transmitter, to the input node of the receiver. The calibration signal is down-converted, with the receiver, to provide a down-converted calibration signal. A discrete Fourier transform is performed on the down-converted calibration signal. Finally, one or more correction factors are determined based on an analysis of the discrete Fourier transform of the down-converted calibration signal. At least one of the correction factors is utilized to facilitate substantial cancellation of a direct current offset associated with the transceiver.

Abstract: A technique for calibrating a transceiver of a wireless communication device includes selectively coupling an output node of a transmitter of the transceiver to an input node of a receiver of the transceiver. A calibration signal is provided, from the output node of the transmitter, to the input node of the receiver. The calibration signal is down-converted, with the receiver, to provide a down-converted calibration signal. A discrete Fourier transform is performed on the down-converted calibration signal. Finally, one or more correction factors are determined based on an analysis of the discrete Fourier transform of the down-converted calibration signal. At least one of the correction factors is utilized to facilitate substantial cancellation of a direct current offset associated with the transceiver.

Abstract: A multi-mode transmitter architecture is configurable for multiple modulation modes using either polar or polar-lite modulation. Multiplexed signal paths and reconfigurable components are controlled for performance in GMSK and EDGE burst modes. Polar-lite EDGE modulation is programmed by setting a multiplexer coupling a first amplitude modulated signal path with a frequency modulated signal path input to a dual-mode power amplifier for amplification of the combined EDGE transmission signal. In full-polar EDGE modulation, amplitude modulated signal is multiplexed into a second amplitude modulated signal path for A/D conversion and comparison with a polar feedback signal coupled from the power amplifier output. The resulting comparison is applied to a power control port of the power amplifier to amplitude modulate the EDGE transmission output. Multiplexers are configured to disconnect the amplitude modulated paths when operating in GMSK signaling for both full-polar and polar-lite modulation.

Abstract: Systems and techniques are described for applying a polar bias modulation having a phase component and an amplitude component to a signal amplified by a power amplifier. The power amplifier (PA) has a plurality of amplifier gain stages and is configured to amplify an input to create an amplifier output signal. The input to the power amplitude is phase modulated based upon the phase component of the polar bias modulation, but need not be amplitude modulated. Amplitude modulation is provided by logic that includes a detector configured to receive an indication of the amplifier output as a feedback signal, a control module configured to generate a control signal based upon both the feedback signal and the amplitude component of the polar bias modulation, and a bias circuit configured to adjust a bias signal associated with at least one of the plurality of amplifier gain stages in response to the control signal.

Abstract: A transmitter (100) includes a fractional N synthesizer, a baseband digital modulation stage coupled to the fractional N synthesizer in a first modulation mode, and a baseband I/Q modulation stage also coupled to the fractional N synthesizer and reusing the fractional N synthesizer in a second modulation mode. A method (300) of operating a transmitter includes transmitting a first signal from a transmitter using the fractional N synthesizer and the baseband digital modulation stage to modulate the first signal according to a first wireless protocol. The method (300) also includes transmitting a second signal from the transmitter using the baseband I/Q modulation stage and the fractional N synthesizer to modulate the second signal according to a second wireless protocol.

Abstract: A frequency generation circuit includes an oscillator (403), a comparator (413) coupled to the oscillator, a first divider (407) coupled to the comparator, a PLL (400) coupled to the first divider, a second divider (422) coupled to the PLL, a first multiplexor (409) coupled to the second divider, a third divider (408) coupled to the comparator and the first multiplexor, a second multiplexor (410) coupled to the comparator and the reference clock PLL, a fourth divider (411) coupled to the second multiplexor, a fifth divider (412) coupled to the comparator, and a seventh divider (450) coupled to the comparator. A method of operating a transceiver includes using the frequency generation circuit to provide a first clock signal, a second clock signal, a first reference frequency, and a second reference frequency for a first component, a second component, a third component, and a fourth component, respectively, of the transceiver.

Abstract: A phase lock loop (100) includes a dual-state charge pump (120) having a first current source (220), a second current source (230) coupled in series to the first current source, a third current source (240), a fourth current source (250) coupled in series to the third current source, and control circuitry (210) coupled to the first, second, third, and fourth current sources. The charge pump can be programmed to be in an adapt mode with large up and down currents or in a normal mode with small up and down currents. The duration of the adapt mode can be programmed by a timer. The phase lock loop has a wide loop bandwidth and a faster lock time during the adapt mode and a narrow loop bandwidth and less phase noise during the normal mode.

Abstract: A device having battery-save circuitry includes a power-on reset circuit (603), an OR-gate (604) coupled to the power-on reset circuit (603), a current-boost timer circuit (602) coupled to the OR-gate (604), a reference oscillator (403) with a start-up current mode enabled by the current-boost timer circuit (602), and a low current secondary reference oscillator (613). A method of operating the device includes operating the device in a battery-save mode and an active mode. A first clock signal is used as a microprocessor clock signal while operating the device in the battery-save mode, and a second or third clock signal is used as the microprocessor clock signal while operating the device in the active mode.

Abstract: A single-chip transceiver integrated circuit (100) has multiple on-chip circuits that implement receiver functions, transmitter functions, and audio processing functions. The IC (100) has interfaces (220, 240, 252, 270, 260, 245, 288, 290) which are situated among the on-chip circuits, and which couple one on-chip circuit to another. At least some of these on-chip interfaces (220, 240, 245, 252, 270) are configurable to couple an off-chip processing circuit to substitute for a corresponding on-chip circuit. In the preferred embodiment, the single-chip transceiver IC (100) supports radio configurations having off-chip versions of corresponding on-chip circuits for performing receiver front-end functions, synthesizer functions, reference oscillator functions, and audio processing functions.

Abstract: A radio (100) having an integrated transceiver circuit (102) avoids circuit crosstalk through the use of a clock shifter circuit (120). The radio includes a microcontroller unit (MCU) (104) controlled by a MCU clock. A channel selector (116) coupled to the MCU (104) provides a selected frequency channel while memory (106) downloads channel information which includes integer clock shifter ratios assigned to each channel. The integrated transceiver (102) includes a clock shifter circuit (120) which divides a reference signal into a clock frequency and provides this clock frequency to the MCU (104) as the MCU clock. The MCU (104) reprograms the clock shifter circuit (120) with one of the integer clock shifter ratios to generate a shifted MCU clock frequency if the selected frequency channel is susceptible to harmonics of the MCU clock.

Abstract: A wideband phase-lock loop frequency synthesizer (200) used in a radio transceiver capable of being reconfigured to operate in either a transmit, receive, or battery save mode. The wideband phase-lock loop frequency synthesizer (200) includes, a divide-by-two divider (205), quadrature detector (204), offset VCO (209) and offset mixer (207) for generating a quadrature phase modulated signal. Moreover, a programmable filter (211) is used for removing predetermined harmonic components of the offset mixed signal enabling the synthesizer to operate over a wide frequency range.

Abstract: Receiver section (200) includes a compensation network (202) which compensates for undesired effects caused by synthesized LO (204). Compensation network (202) substantially duplicates the amplitude and phase delay of synthesized LO (204) allowing for a substantially flat demodulated frequency response to be achieved at output (122) which is independent of the bandwidth of synthesized LO (204).

Abstract: A helical cavity resonator having a grounded shield, a hollow coil form and associated quarter wavelength wire coil. A non-ferrous conductive slug can be adjusted to variable positions inside the hollow coil form. Placement of the slug in a region proximate to the inside of the wire coil tunes the cavity resonator in a predominately inductive manner. Changing the slug position in the bore so that it is proximate to the shield top and removed from the inside of the wire coil tunes the cavity resonator in a predominately capacitive manner. By utilizing both inductive and capacitive tuning a helical cavity resonator with a wide tuning range is realized while maintaining a simple, inexpensive construction.