Abstract: A structure and related method for determining the uncertainty window associated with clock signals on a microprocessor using circuitry on the microprocessor die itself and external software. A target clock signal of interest is compared to a series of reference clock signals having the same frequency, but differing in phase relationship. Where the target clock signal makes state transitions with respect to the various reference clock signals over the course of several thousand comparisons is indicative of the uncertainty window for that target clock. By adjusting the phase relationship between the reference clock signals, and thereby adjusting the width of the time windows defined by corresponding features of the reference clock signals, the uncertainty window for the target clock signal may be iteratively determined.

Abstract: A structure and related method for determining the uncertainty window associated with clock signals on a microprocessor using circuitry on the microprocessor die itself and external software. A target clock signal of interest is compared to a series of reference clock signals having the same frequency, but differing in phase relationship. Where the target clock signal makes state transitions with respect to the various reference clock signals over the course of several thousand comparisons is indicative of the uncertainty window for that target clock. By adjusting the phase relationship between the reference clock signals, and thereby adjusting the width of the time windows defined by corresponding features of the reference clock signals, the uncertainty window for the target clock signal may be iteratively determined.

Abstract: A clock distribution system for a semiconductor device provides for both on-chip and in-package clock distribution via on-chip and in-package clock distribution networks. Each of these networks is selectively enabled depending on the mode of operation. Specifically, for wafer testing, the on-chip clock distribution network is selected. Thus, a probe tester need only provide a single clock source with conventional timing specifications to test the operation of the chip. In contrast, during normal operation, an in-package clock distribution network is enabled. In-package clock routing provides the lowest variation mode and thus, will result in the maximum clock frequency for the chip.

Abstract: A remote delay regulator circuit measures the effects of intrinsic propagation delays experienced by a system clock signal propagating through an extended clock distribution path that encompasses a clock repeater chip, a module transmission network and a clock distribution network of an integrated circuit (IC) chip. Delay measurement of the associated (IC) chips on the module is provided by sensing the clock signal at the beginning of the network and at the end of the network. The BEFORE and AFTER sense taps are routed to a signal generation circuit on the repeater chip where measurement signals are generated that define the beginning and end of a measurement cycle. A clock delay path circuit on the repeater chip contains the logic circuitry required to measure and compensate for the actual measured intrinsic propagation delays of the total clock transmission network.

Abstract: An "absolute" delay regulator of a clock repeater chip performs a precise measurement of the propagation delay of a clock signal and adjusts that delay so as to maintain a fixed-phase relationship with an input clock signal. A replica loop accurately replicates the internal path and external loading, including input and output buffers, of the chip. The output of the replica loop drives a delay line whose tapped outputs provide an absolute delay measurement. Results of the measurement are decoded and used to select an appropriate tap to another delay line used to insert a desired amount of delay to an output clock signal.

Abstract: An update synchronizer includes a two-stage synchronization unit for generating enable signals to select an output signal from among multiple input clock signals of a clock delay multiplexer. The enable signals originate from an asynchronous control signal having a phase different from that of the clock signals. A pre-synchronization logic stage transforms the asynchronous control signal into complementary synchronous control signals for use by the clock synchronization units; these synchronous control signals, in turn, are transformed into complementary selection enable signals having phases within the domains of the input clock signals. This ensures that transitions of the enable signals occur during the same clock period.

Abstract: An "absolute" delay regulator of a clock repeater chip performs a precise measurement of the propagation delay of a clock signal and adjusts that delay so as to maintain a fixed-phase relationship with an input clock signal. A replica loop accurately replicates the internal path and external loading, including input and output buffers, of the chip. The output of the replica loop drives a delay line whose tapped outputs provide an absolute delay measurement. Results of the measurement are decoded and used to select an appropriate tap to another delay line used to insert a desired amount of delay to an output clock signal.

Abstract: A test register coupled to an absolute delay regulator circuit of a clock repeater chip enables complete functional testing of a clock delay path of the regulator. The test register is connected to a measurement latch of the clock path in a "logical OR" configuration with respect to a measurement delay line and is enabled during a test mode by control logic of the repeater chip. Operationally, a sequence of logic "0" bits are forced in the measurement delay line during test mode. A state machine clears the measurement latch, and then loads a test pattern into the test register. As each bit of the register is set, a corresponding bit in the measurement latch is also set to simulate a measurement cycle; the results of the "measurement" are stored in the measurement latch. Once the test pattern is loaded, the repeater chip is placed into a measurement test mode. Execution of a measurement test cycle then propagates the test pattern throughout the clock delay path of the regulator.

Abstract: An AWTSS is shown to be made up of an improved synthetic aperture radar (SAR) for generating radar maps with various degrees of resolution required for navigation of an aircraft and detection of ground targets in the presence of electronic countermeasures and clutter. The SAR consists, in effect, of four frequency-agile radars sharing quadrants of a single array antenna mounted within a radome of a "four axis" gimbal with a sidelobe cancelling subarray mounted at the phase center of each quadrant. Motion sensors are also mounted on the single array antenna to provide signals for compensating for vibration and stored compensating signals are used to compensate for radome-induced errors. In addition, a signal processor is shown which is selectively operable to generate radar maps of any one of a number of desired degrees of resolution, such processor being adapted to operate in the presence of clutter or jamming signals.

Abstract: A field effect transistor (FET) logic gate wherein a plurality of FETs is coupled to an output enhancement mode FET through a noise immunity circuit, such noise immunity circuit including a Schottky diode. A biasing network ensures that any conducting one of the input transistors produces a forward voltage drop between its input and output less than the forward drop of the Schottky diode circuit ensuring that the voltage at the gate electrode of the output transistor is less than the threshold voltage of such output transistor in the presence of noise. In one embodiment the logic gate includes a coupling FET having a gate electrode coupled to the gate electrode of the output transistor through the noise immunity Schottky diode circuit, and a source electrode coupled to the plurality of input transistors.