Abstract: An analog-to-digital converter compensating apparatus and associated methods are provided. The apparatus can include an ADC, a state-slope sampler responsive to output data of the ADC to produce a state sample and a slope sample, a compensator which can include memory having an error-table associated therewith to provide an error or compensation sample to a combiner which combines the compensation sample with the state value to provide a compensated ADC output, and a compensator error processor positioned to receive the state sample, the slope sample, and an updated error value to dynamically update the compensator and thereby dynamically update the compensated ADC output.

Abstract: Filter coefficients of a beamformer are computed based on a segment of input samples. The segment of input samples is divided into a plurality of blocks of input samples wherein the plurality of blocks of input samples are received by a shared memory at a first rate. The first block of the plurality of blocks is received in the shared memory at a first time. The plurality of blocks of input samples from the shared memory are read out at a second rate wherein the first block of the plurality of blocks is read from the shared memory at a second time. A plurality of partial covariance matrices for the plurality of blocks read from the shared memory are computed and added together to determine a covariance matrices used to compute the filter coefficients.

Abstract: A method and apparatus are described for a networked lighting system that may be controlled either remotely or locally by a power line communication (PLC) link. The components of the system, addressable lamp ballasts and addressable wall switches, replace their conventional counterparts. The resulting networked lighting system implemented with these components is controlled remotely from a centralized building control center. A particular room may be controlled by the building control center or locally by a wall switch. The invention requires no rewiring of the building's wiring plant, because the addressable components are direct electrical replacements, and installation of the system, therefore, takes a minimum amount of time.

Abstract: A method and apparatus are described for a networked lighting system that may be controlled either remotely or locally by a power line communication (PLC) link. The components of the system, addressable lamp ballasts and addressable wall switches, replace their conventional counterparts. The resulting networked lighting system implemented with these components is controlled remotely from a centralized building control center. A particular room may be controlled by the building control center or locally by a wall switch. The invention requires no rewiring of the building's wiring plant, because the addressable components are direct electrical replacements, and installation of the system, therefore, takes a minimum amount of time.

Abstract: A method and computer program product are disclosed for locating signal jammers in a digital beamforming receiver having an antenna with a plurality of associated antenna orientations. An associated antenna gain value is calculated for a first of a sequence of the plurality of antenna orientations at each of a series of sample points. The antenna gain values from the first antenna orientation are evaluated for null spaces to obtain a set of candidate null locations. Associated antenna gain values are calculated and evaluated for subsequent antenna orientations only at the set of candidate null locations. Candidate null locations are eliminated from the set after any evaluation in which they are not found to be null spaces.

Abstract: Filter coefficients of a beamformer are computed based on a segment of input samples. The segment of input samples is divided into a plurality of blocks of input samples wherein the plurality of blocks of input samples are received by a shared memory at a first rate. The first block of the plurality of blocks is received in the shared memory at a first time. The plurality of blocks of input samples from the shared memory are read out at a second rate wherein the first block of the plurality of blocks is read from the shared memory at a second time. A plurality of partial covariance matrices for the plurality of blocks read from the shared memory are computed and added together to determine a covariance matrices used to compute the filter coefficients.

Abstract: A frequency-shift keying (FSK) demodulator demodulates a binary signal encoded in an FSK signal. The present invention employs a bandpass filter to filter out noise and pass the frequencies used in the modulation. A comparitor converts the received signal into a square wave. A divider reduces the frequency of the square wave signal by a dividing factor. A counter counts the number of square wave transitions in a predetermined time period. A decision device receives the dividing factor from the divider, and uses this factor to adjust the count measured. The adjusted count is compared to counts pertaining to modulated frequencies to select a frequency. A bit value associated with the selected frequency is output for the time period being demodulated.

Abstract: Directional antennae on aircraft and on cellular telephone base stations, having a polarity opposite that of potentially interfering ground system signals, minimize signal strength of air cellular signals received by ground cellular stations. Aircraft directional antennae comprise patch antennae or vertical arrays of loop elements or vertical arrays of virtual loop elements. Additionally, air cellular signals are switched to channels not currently in use by ground cellular systems.

Abstract: A symbol synchronizer derives a symbol clock reference from a sampled baseband signal which may be of a variety of suitable digital signalling formats, including non-return-to-zero (NRZ) and Manchester formats. A one-bit quantizer receives the sampled signal and provides a binary representation thereof to a level-transition detector which generates a sequence of pulses at the symbol rate of the binary-valued data sequence and at a predetermined timing offset from the symbol timing epochs of the data sequence. The timing offset depends on the digital signalling format and is on the interval ##EQU1## where T is the symbol period. The level-transition detector employs delay circuitry, logic circuitry, and a monostable multivibrator to mask transitions in the quantized data sequence that do not occur at the predetermined timing offset from the timing epochs and to generate the symbol clock pulse sequence.