Patents by Inventor Richard Cliff
Richard Cliff has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180308614Abstract: Design and construction is described for remotely-controllable variable MRI-compatible low-noise inductors and capacitors, each having a wide variation range and each occupying a volume of no more than 30 cubic centimeters. To optimize noise figure in 3-tesla medical MRI antenna arrays, an exemplar capacitor is connected in series following an antenna element and an exemplar inductor is connected in shunt following an exemplar capacitor. Exemplar Inductors are constructed as a pair of flux-coupled coils which are connected by a movable or rotatable contactor positioned by folded and nested stepping mechanisms. Exemplar inductors are constructed from two flux-coupled parallel solenoid coils or from two flux-coupled toroid-segment coils. Exemplar capacitors are designed and constructed in an analogous manner. Other miniature inductor and capacitor embodiments are possible. Miniature variable resistor embodiments can be constructed in a manner analogous to that of the capacitors.Type: ApplicationFiled: June 24, 2018Publication date: October 25, 2018Inventor: Richard Cliff
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Publication number: 20180028691Abstract: Described are methods for the detection, in the eye of an individual, of protein aggregates or other misfolded proteins associated with disease using peptide or peptide mimic probes that preferentially associate with the protein aggregates or misfolded proteins, which can be accomplished non-invasively.Type: ApplicationFiled: October 13, 2017Publication date: February 1, 2018Applicant: SYSTEM OF SYSTEMS ANALYTICS, INC.Inventors: Giora FEUERSTEIN, Richard Cliff
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Patent number: 9795692Abstract: Described are methods for the detection, in the eye of an individual, of protein aggregates or other misfolded proteins associated with disease using peptide or peptide mimic probes that preferentially associate with the protein aggregates or misfolded proteins, which can be accomplished non-invasively.Type: GrantFiled: June 5, 2014Date of Patent: October 24, 2017Assignee: SYSTEM OF SYSTEMS ANALYTICS, INC.Inventors: Giora Feuerstein, Richard Cliff
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Publication number: 20150125396Abstract: Described are methods for the detection, in the eye of an individual, of protein aggregates or other misfolded proteins associated with disease using peptide or peptide mimic probes that preferentially associate with the protein aggregates or misfolded proteins, which can be accomplished non-invasively.Type: ApplicationFiled: June 5, 2014Publication date: May 7, 2015Applicant: Adlyfe, Inc.Inventors: Giora Feuerstein, Richard Cliff
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Publication number: 20140354389Abstract: A new family of programmable low-noise RF impedance transformers has been developed. These new transformers can be configured and operated to compensate for variable antenna output impedance. This enables better optimization of RF receiving-system SNR. For some applications, these new devices can be more compact and less expensive than any previously available. In particular, such new transformers can improve MRI system performance. This requires additional new art because MRI systems demand components which are not ferromagnetic, which do not produce spurious MR signals and which add very little noise to received RF signals. In various embodiments, these new transformers are comprised of remotely-controlled variable capacitors and inductors which are connected in networks between antenna element outputs and their following LNA inputs. These new step-programmable inductors and capacitors can be either electrically or pneumatically actuated.Type: ApplicationFiled: May 30, 2013Publication date: December 4, 2014Inventor: Richard Cliff
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Patent number: 8407649Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.Type: GrantFiled: May 10, 2012Date of Patent: March 26, 2013Assignee: Altera CorporationInventors: Andy L. Lee, Cameron McClintock, Brian Johnson, Richard Cliff, Srinivas Reddy, Christopher Lane, Paul Leventis, Vaughn Timothy Betz, David Lewis
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Publication number: 20120217998Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.Type: ApplicationFiled: May 10, 2012Publication date: August 30, 2012Applicant: ALTERA CORPORATIONInventors: Andy L. Lee, Cameron McClintock, Brian Johnson, Richard Cliff, Srinivas Reddy, Christopher Lane, Paul Leventis, Vaughn Timothy Betz, David Lewis
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Patent number: 8201129Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.Type: GrantFiled: May 13, 2009Date of Patent: June 12, 2012Assignee: Altera CorporationInventors: Andy L. Lee, Cameron McClintock, Brian Johnson, Richard Cliff, Srinivas Reddy, Chris Lane, Paul Leventis, Vaughn Timothy Betz, David Lewis
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Publication number: 20090224800Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.Type: ApplicationFiled: May 13, 2009Publication date: September 10, 2009Applicant: ALTERA CORPORATIONInventors: Andy L. Lee, Cameron McClintock, Brian Johnson, Richard Cliff, Srinivas Reddy, Chris Lane, Paul Leventis, Vaughn Timothy Betz, David Lewis
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Patent number: 7584447Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.Type: GrantFiled: August 12, 2005Date of Patent: September 1, 2009Assignee: Altera CorporationInventors: Andy L. Lee, Cameron McClintock, Brian Johnson, Richard Cliff, Srinivas Reddy, Chris Lane, Paul Leventis, Vaughn Timothy Betz, David Lewis
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Publication number: 20070200596Abstract: A programmable logic device (PLD) includes at least two regions. Each region includes electrical circuitry that has a set of transistors. Each of the two regions has a corresponding fixed transistor threshold voltage, a corresponding fixed transistor body bias, and a corresponding fixed supply voltage.Type: ApplicationFiled: February 24, 2006Publication date: August 30, 2007Inventors: Andy Lee, Christopher Lane, Ketan Zaveri, Richard Cliff, Cameron McClintock, Srinivas Reddy, David Lewis
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Patent number: 7164903Abstract: An integrated N-way Wilkinson power divider is described. In one embodiment, the N-way Wilkinson power divider uses a conductor layer with a cross-over (or cross-under) resistor insulated from the conducting layer by an insulating bridge. In one embodiment, the width of the transmission line underneath a cross-over resistor is adjusted to improve performance In one embodiment, a three-way Wilkinson power divider is formed using microstrip transmission lines on a single-layer substrate that supports the microstrip transmission lines, dielectric insulators, and resistors.Type: GrantFiled: June 10, 2003Date of Patent: January 16, 2007Assignee: Smiths Interconnect Microwave Components, Inc.Inventors: Richard Cliff, Michael J. Kettner, Robert J. Wright, Andrew J. Kettner, Patrick A. Biebersmith, Juan G. Ayala
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Publication number: 20070011578Abstract: A device reduces false positive memory error detections by using a masking unit and sensitivity mask data to exclude unused portions of the memory from the error detection computations. A device includes an error detection unit to read data from the memory and verify data integrity. The sensitivity mask data indicates unused portions of the memory. Unused portions of the memory may correspond with configuration data for unused portions of a programmable device. Each bit of the sensitivity mask data may indicate the usage of one or more bits of the data from the memory. In response to the mask data, the masking unit sets data from the unused portions of the memory to values that do not change the result of the error detection computations. This prevents any errors in data from the unused portions of the memory from raising an error signal.Type: ApplicationFiled: April 19, 2006Publication date: January 11, 2007Applicant: Altera CorporationInventors: David Lewis, Robert Blake, Richard Cliff, Srinivas Reddy
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Publication number: 20070008000Abstract: Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE-Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.Type: ApplicationFiled: August 1, 2006Publication date: January 11, 2007Inventors: Andy Lee, Wanli Chang, Cameron McClintock, John Turner, Brian Johnson, Chiao Hwang, Richard Chang, Richard Cliff
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Patent number: 7161381Abstract: A programmable logic device (PLD) includes a first memory block and at least a second memory block, where the two memory blocks have different memory sizes.Type: GrantFiled: February 25, 2004Date of Patent: January 9, 2007Assignee: Altera CorporationInventors: Srinivas Reddy, David Jefferson, Christopher F. Lane, Vikram Santurkar, Richard Cliff
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Patent number: 7058920Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.Type: GrantFiled: June 11, 2003Date of Patent: June 6, 2006Assignee: Altera CorporationInventors: Andy L. Lee, Cameron McClintock, Brian Johnson, Richard Cliff, Srinivas Reddy, Chris Lane, Paul Leventis, Vaughn Timothy Betz, David Lewis
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Publication number: 20060033527Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.Type: ApplicationFiled: August 12, 2005Publication date: February 16, 2006Inventors: Andy Lee, Cameron McClintock, Brian Johnson, Richard Cliff, Srinivas Reddy, Chris Lane, Paul Leventis, Vaughn Betz, David Lewis
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Patent number: 6970014Abstract: An embodiment of this invention pertains to a 3-sided routing architecture to interconnect function blocks, such as logic array blocks (“LABs”), within a programmable logic device (“PLD”). In the 3-sided routing architecture, inputs and outputs on a first side of a function block connect to a first channel, and inputs and outputs on a second side of the function block connect to a second channel where the second side is opposite the first side. Inputs and outputs on a third side of the function block connect to a third channel. A fourth channel associated with a fourth side of the function block, the fourth side opposite the third side, is coupled only to the first channel and the second channel. In one configuration, the inputs and outputs on each of the first side, the second side, and the third side have an equal number of inputs and outputs. In this configuration, each of the first channel, the second channel, and the third channel have the same width.Type: GrantFiled: July 21, 2003Date of Patent: November 29, 2005Assignee: Altera CorporationInventors: David M. Lewis, Paul Leventis, Andy L. Lee, Brian D. Johnson, Richard Cliff, Srinivas T. Reddy, Christopher F. Lane, Cameron R. McClintock, Vaughn Betz, Chris Wysocki, Alexander R. Marquardt
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Publication number: 20050151564Abstract: Circuitry is provided to individually configure each I/O of an integrated circuit to be compatible with a different LVTTL I/O standards. This can be done with only one I/O supply voltage, where that voltage is the highest of the I/O voltages needed in a particular application. The circuitry operates by regulating the output voltage of the I/O cell so that it is above the VOH and below the maximum VIH for the LVTTL standard for which it will comply with. Since each I/O cell is individually configurable, any I/O can drive out to any LVTTL specification.Type: ApplicationFiled: December 3, 2004Publication date: July 14, 2005Applicant: Altera CorporationInventors: Cameron McClintock, Richard Cliff, Bonnie Wang
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Patent number: 6895570Abstract: An embodiment of this invention pertains to a wire that interconnects multiple function blocks within a programmable logic device (“PLD”). An electrically optimum physical length is determined for the wire. A wire having the electrically optimum physical length transmits a signal down the wire as fast as possible. Some of the wires used in the PLD have a physical length substantially the same as the electrically optimum physical length or an adjustment of the electrically optimum physical length to account for non-electrical considerations. The physical length, as used herein, is the measured length of the wire. A logical length of the wire, as used herein, is the number of function blocks that the wire spans. Given that the function blocks have a different height and width, the logical length of the wire varies depending on the orientation of the wire. A routing architecture is an array that includes rows and columns of function blocks.Type: GrantFiled: January 25, 2002Date of Patent: May 17, 2005Assignee: Altera CorporationInventors: David M. Lewis, Vaughn Betz, Paul Leventis, Michael Chan, Cameron R. McClintock, Andy L. Lee, Christopher F. Lane, Srinivas T. Reddy, Richard Cliff