Abstract: Methods and apparatus for decision feedback equalization with dithered updating are disclosed. An example method to equalize a received signal sample representative of a digital quantity disclosed herein comprises selecting a slicing level from a plurality of slicing levels to detect the digital quantity represented by the received signal sample, and deciding whether to update the selected slicing level based on whether a previously determined pseudorandom number of signal samples were received before receipt of the received signal sample and after a previous slicing level update.

Abstract: Methods and apparatus for decision feedback equalization with dithered updating are disclosed. An example method to equalize a received signal sample representative of a digital quantity disclosed herein comprises selecting a slicing level from a plurality of slicing levels to detect the digital quantity represented by the received signal sample, and deciding whether to update the selected slicing level based on whether a previously determined pseudorandom number of signal samples were received before receipt of the received signal sample and after a previous slicing level update.

Abstract: A content addressable memory (CAM) system (50) is disclosed which includes a CAM array (52) for storing an array of data words. More than one data word is stored on each row with the bits of the data word columns interleaved with each other. The CAM array (52) is accessed during one of several modes of operation in accordance with signals from a bit line controller (54) which activate certain ones of a plurality of bit lines coupling the bit line controller (54) to the CAM array (52). The modes of operation, as indicated by a mode control signal, include a write mode, a read mode and a match mode. In first embodiment of the present invention, the bit line controller (54) sequentially accesses each of the columns of data words by selectively activating certain of the bit lines in accordance with a column address signal and the mode control signal.

Abstract: An electronic device having addressable storage elements and a bus so that the storage elements are accessible via the bus, an address register connected to the bus, a data register connected to the bus, terminals for serial scan-in and scan-out, a scanable emulation control register coupled to the terminals, and a selecting circuit responsive to bits in the emulation control register for coupling the address register and the data register to the terminals to enable scanning of the address and data registers.