Abstract: A surgical instrument includes an anvil and an elongate channel. The elongate channel includes a plurality of first electrical contacts and a plurality of electrical connectors comprising a plurality of second electrical contacts, wherein the electrical connectors are spring-biased such that a gap is maintained between the first electrical contacts and the second electrical contacts. The surgical instrument further includes a staple cartridge releasably attachable to the elongate channel, wherein the staple cartridge has a cartridge body comprising a plurality of staple cavities, a plurality of staples deployable from the staple cavities into the tissue, and a plurality of third electrical contacts, wherein the attachment of the staple cartridge to the elongate channel moves the electrical connectors causing the second electrical contacts to bridge the gap and become electrically coupled to the first electrical contacts.

Abstract: Still frame detection for single pass video data, including: determining that an average quantization parameter of a frame of video data falls below a quantization parameter threshold; determining whether an amount of skipped macroblocks in the frame meets a skipped macroblock threshold; and responsive to the amount of skipped macroblocks exceeding the skipped macroblock threshold, identifying the frame as a still frame.

Abstract: A technique for operating a processing device is disclosed. The method includes configuring at least one switch to interconnect one or more selected IP to the processing device, receiving an activation signal associated with the at least one switch based on the one or more selected IP, in response to the activation signal, causing the at least one switch to disable connection to the one or more selected IP, and verifying access to the one or more selected IP is disabled.

Abstract: A technique for performing convolution operations is disclosed. The technique includes performing a first convolution operation based on a first convolutional layer input image to generate at least a portion of a first convolutional layer output image; while performing the first convolution operation, performing a second convolution operation based on a second convolutional layer input image to generate at least a portion of a second convolutional layer output image, wherein the second convolutional layer input image is based on the first convolutional layer output image; storing the portion of the first convolutional layer output image in a first memory dedicated to storing image data for convolution operations; and storing the portion of the second convolutional layer output image in a second memory dedicated to storing image data for convolution operations.

Abstract: Methods and systems are disclosed for emulating, in a platform, the performance of a target platform. Techniques disclosed include receiving, by the platform, values of system features, associated with a target performance of the target platform; and setting, by the platform, one or more configuration knobs, based on the received values of system features, to match a performance of the platform to the target performance of the target platform.

Abstract: A technique for operating a memory system is disclosed. The technique includes performing a first request, by a first memory client, to access data at a first memory address, wherein the first memory address refers to data in a first memory section that is coupled to the first memory client via a direct memory connection; servicing the first request via the direct memory connection; performing a second request, by the first client, to access data at a second memory address, wherein the second memory address refers to data in a second memory section that is coupled to the first client via a cross connection; and servicing the second request via the cross connection.

Abstract: A technique for operating a processing device is disclosed. The method includes irreversibly activating a testing mode switch of the processing device; in response to the activating, entering a testing mode in which normal operation of the processing device is disabled; receiving software for the processing device in the testing mode; based on whether the software is verified as testing mode-signed software, executing or not executing the software.

Abstract: Still frame detection for single pass video data, including: determining that an average quantization parameter of a frame of video data falls below a quantization parameter threshold; determining whether an amount of skipped macroblocks in the frame meets a skipped macroblock threshold; and responsive to the amount of skipped macroblocks exceeding the skipped macroblock threshold, identifying the frame as a still frame.

Abstract: For one or more stages of execution of a software application at a first processor, a remap vector of a second processor is reconfigured to represent a dynamic mapping of virtual address groups to physical address groups for that stage. Each bit position of the remap vector is configured to store a value indicating whether a corresponding virtual address group is actively mapped to a corresponding physical address group. Address translation operations issued during a stage of execution of the software application are selectively processed based on the configuration of the remap vector for that stage, with the particular value at the bit position of the remap vector associated with the corresponding virtual address group controlling whether processing of the address translation operation is continued to obtain a virtual-to-physical address translation sought by the address translation operation or processing of the address translation operation is ceased and a fault is issued.

Abstract: For one or more stages of execution of a software application at a first processor, a remap vector of a second processor is reconfigured to represent a dynamic mapping of virtual address groups to physical address groups for that stage. Each bit position of the remap vector is configured to store a value indicating whether a corresponding virtual address group is actively mapped to a corresponding physical address group. Address translation operations issued during a stage of execution of the software application are selectively processed based on the configuration of the remap vector for that stage, with the particular value at the bit position of the remap vector associated with the corresponding virtual address group controlling whether processing of the address translation operation is continued to obtain a virtual-to-physical address translation sought by the address translation operation or processing of the address translation operation is ceased and a fault is issued.

Abstract: A digital multimeter having automatic function selection capability includes a signal type detector and an analog-to-digital converter formed as an application specific integrated circuit. The signal type detector has a comparator circuit that compares the analog input signal to be measured with predetermined thresholds and stores the resulting values, which are related to the type of analog input signal, in a memory that is also a part of the signal type detector. A controller executes an automatic function selection program that causes the controller to read the stored values and generate a corresponding function code, which causes an analog-to-digital converter to be configured to perform an appropriate conversion function on the analog input signal. When a change in the type of analog input signal is sensed, the controller aborts the present measurement cycle and proceeds with a next measurement cycle in which the changed analog input signal is measured.

Abstract: The capacitance of an unknown capacitor is measured with multimeter instrumentation employing a dual slope analog-to-digital converter. The initial voltage across the capacitor is measured and the capacitor is cyclically charged until the capacitor reaches a predetermined proportion of possible charge. The final voltage is measured. The voltage across the charging resistance is integrated over successive charging cycles to provide a value proportional to the charge delivered to the capacitor and this value is divided by the difference between the initial and final voltages.

Abstract: Disclosed is a digital multimeter having an automatic function selection capability. The device includes a sensing circuit connected to its input to respond to the type of analog signal which is sensed and to provide logic signals which are characteristic thereof. These logic signals may be utilized to cause generation of encoding signals to encode and dispose the converter circuit to perform the desired conversion function and provide the desired display as a function of the analog input. The device may include an internal reference signal source such as a DC reference potential and the sensing circuit may sense a differential between such reference source and the external analog signal to make a determination to utilize or disconnect the reference signal source in performing the function dictated by the nature of the analog signal.

Abstract: An apparatus for and a method of measuring capacitance employs a charge measuring system. While a capacitive element, which may be an unknown capacitor, is charged completely to a predetermined voltage, a charge proportional to the capacitance of the capacitive element is accumulated on the feedback capacitor of an integrating operational amplifier. Thereafter, the charge is measured by measuring the time required to completely remove the charge from the feedback capacitor using the same predetermined voltage as a reference. In a preferred embodiment, the present invention is manifested as a capacitance measurement feature in a hand-held multimeter wherein a largely conventional dual-slope analog-to-digital converter is employed as the charge measuring system.

Abstract: There is provided according to the invention a method and apparatus for eliminating or minimizing the error due to amplifier offset or drift error in an integrating dual slope analog-to-digital converter. The converter is provided with a switching and control arrangement whereby the integrating capacitor is charged for one-half of the predetermined charging time as a function of the sum of the levels of the unknown signal and the error signal. The integrating capacitor is charged for the remaining half of the predetermined time period as a function of the difference of the levels of the unknown signal and the error signal so that the capacitor reaches a level of charge which is a function of the level of the unknown signal substantially unaffected by the level of the error signal.

Abstract: A dual slope analog to digital (A/D) converter starts by auto zeroing and making a number of high speed A/D samples before auto zeroing again. A microprocessor causes output of the high speed samples for a bar graph and applies predetermined correction factors to allow accumulation of the high speed samples to provide a high accuracy numerical output.

Abstract: There is provided according to the invention a method and apparatus for eliminating or minimizing the error due to amplifier offset or drift error in an integrating dual slope analog-to-digital converter. The converter is provided with a switching and control arrangement whereby the integrating capacitor is charged for one-half of the predetermined charging time as a function of the sum of the levels of the unknown signal and the error signal. The integrating capacitor is charged for the remaining half of the predetermined time period as a function of the difference of the levels of the unknown signal and the error signal so that the capacitor reaches a level of charge which is a function of the level of the unknown signal substantially unaffected by the level of the error signal.