Abstract: Systems, methodologies, computer-readable media, and other embodiments associated with ordering instructions are described. One exemplary system embodiment can include an analysis logic configured to analyze executable instructions from an executable program. A re-write logic can be configured to re-order selected load instructions within the executable program based on latency times for the selected load instructions.

Abstract: A method for optimizing a code section prior to performing register allocation for variables referenced in the plurality of computer instructions. The method includes performing at least one of a full prematerialization or a partial prematerialization for a variable in the plurality of computer instructions. The full prematerialization replaces the variable in every use of the variable in the plurality of computer instructions with one or more variants of the variable and replaces a definition of the variable with a nop instruction. The partial prematerialization replaces some but not all occurrences of the variable in uses of the variable in the plurality of computer instructions with one or more variants of the variable without replacing the definition of the variable with the nop instruction.

Abstract: A compiler configured for optimizing non-loop memory access instructions of a computer program to form architected memory instructions conforming to a base register auto-incrementing addressing mode. The compiler includes code for obtaining an intermediate stream of code containing pseudo-memory instructions from the non-loop memory access instructions. The intermediate stream of code includes at least one place holder instruction preserving a value associated with a base of a first non-loop memory access instruction even after the first non-loop memory instruction is converted to one of the pseudo-memory instructions. The compiler includes code for converting the intermediate stream of code using the intermediate stream of code and the at least one place holder instruction to obtain the architected memory instructions.

Abstract: A method for optimizing a code section prior to performing register allocation for variables referenced in the plurality of computer instructions. The method includes performing at least one of a full prematerialization or a partial prematerialization for a variable in the plurality of computer instructions. The full prematerialization replaces the variable in every use of the variable in the plurality of computer instructions with one or more variants of the variable and replaces a definition of the variable with a nop instruction. The partial prematerialization replaces some but not all occurrences of the variable in uses of the variable in the plurality of computer instructions with one or more variants of the variable without replacing the definition of the variable with the nop instruction.

Abstract: A method of efficient code generation for modulo scheduled uncounted loops includes: assigning a given stage predicate to each instruction in each stage, including assigning a given stage predicate to each instruction in each speculative stage; and using the stage predicate to conditionally enable or disable the execution of an instruction during the prologue and epilogue execution.

Abstract: The present invention is a software pipeline method and system. In one embodiment a software pipeline method commences pipeline operations. If a flow control condition is valid, a branch operation is performed. After the pausing the software pipeline method returns to the pipeline operations at the same point in the pipeline operations at which the pause initiated.

Abstract: A method of efficient code generation for modulo scheduled uncounted loops includes: assigning a given stage predicate to each instruction in each stage, including assigning a given stage predicate to each instruction in each speculative stage; and using the stage predicate to conditionally enable or disable the execution of an instruction during the prologue and epilogue execution.