Patents by Inventor Richard E. Harper

Richard E. Harper has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6675316
    Abstract: A method of (and system for) recovering the state of a failed node in a distributed shared memory system, includes directing a flush of data from a failed node, and flushing the data from the failed node to a memory node.
    Type: Grant
    Filed: July 12, 2000
    Date of Patent: January 6, 2004
    Assignee: International Business Machines Corporation
    Inventor: Richard E. Harper
  • Publication number: 20020144178
    Abstract: A method (and computer system in which at least one software component thereof is restarted based on projection of resource exhaustion), for selecting the most suitable projection method from among a class of projection methods, includes providing M fitting modules which take measured symptom data associated with the system as input and produce M scores, wherein M is an integer, selecting the fitting module producing the best score, and from the selected module, producing a prediction of the resource exhaustion time.
    Type: Application
    Filed: March 30, 2001
    Publication date: October 3, 2002
    Inventors: Vittorio Castelli, Richard E. Harper, Philip Heidelberger
  • Patent number: 6018812
    Abstract: Wafer scale integrated circuitry which uses a cluster of wafer components, each component having a plurality of processing elements and a network element connected thereto for controlling the transfer of information to and from the processing elements. The network element is connected to network elements of other wafer components of the cluster for controlling the transfer of information to and from such other network elements. One or more redundant groups of processing elements are formed on the wafer components of the cluster, each redundant group being configured so that the processing elements in the group reside on different ones of the wafer components.
    Type: Grant
    Filed: October 17, 1990
    Date of Patent: January 25, 2000
    Assignee: 501 Charles Stark Draper Laboratory, Inc.
    Inventors: John J. Deyst, Jr., Richard E. Harper, Jaynarayan H. Lala
  • Patent number: 5269016
    Abstract: A fault tolerant data processing system which provides single fault Byzantine resilience which system uses a number of fault containment regions each of which includes at least one processing element. The fault containment regions of the system are arranged to utilize a shared memory, each of such regions including a portion of the shared memory. The shared memory portion of each fault containment region provides communication with the shared memory portions of each of the other fault containment regions. A shared memory portion includes an encoder for encoding a data byte from the processor in the region into a number of data byte symbols from which the data byte can be reconstructed. The data byte symbols can be stored in the shared memory portion of the region and can be transmitted to one or more of the shared memory portions of the other fault containment regions.
    Type: Grant
    Filed: September 24, 1990
    Date of Patent: December 7, 1993
    Assignee: Charles Stark Draper Laboratory, Inc.
    Inventors: Bryan P. Butler, Richard E. Harper
  • Patent number: 4937741
    Abstract: A system for synchronizing the operation of a plurality of redundant processors forming groups thereof in which a frame of operation is defined as a time period during which a selected number of processing events occurs. For each processor, the performance of a first one of such events specifies the start of a frame and the performance of the last one of such events specifies the end of a frame. When the final event is performed by the last-to-perform of the processors of a group, the operations of all the processors of the group are then synchronized to start the next frame of operation at substantially the same time. The processors have execution rates which lie within the specified range thereof, the processors must perform their final events within a specified time period, and the processors of a group are arranged so as to start a frame of operation within another specified time period.
    Type: Grant
    Filed: April 28, 1988
    Date of Patent: June 26, 1990
    Assignee: The Charles Stark Draper Laboratory, Inc.
    Inventors: Richard E. Harper, Jaynarayan H. Lala
  • Patent number: 4907232
    Abstract: A fault tolerant processing system which includes a plurality of at least (3f+1) fault containment regions each including a plurality of processors and a network element connected to each of the processors and to the network elements of the other regions. Groups of processors are used to form redundant processing sites, the number of each group being included in a different fault containment region. The operations of the network elements are synchronized and the system can be arranged to re-configure the groups of processors so as to form different pluralities of redundant processing sites.
    Type: Grant
    Filed: April 28, 1988
    Date of Patent: March 6, 1990
    Assignee: The Charles Stark Draper Laboratory, Inc.
    Inventors: Richard E. Harper, Jaynarayan H. Lala