Patents by Inventor Richard E. McCullough

Richard E. McCullough has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • III-V Semiconductor growth initiation on silicon using TMG and TEG
    Patent number: 4910167
    Abstract: A GaAs containing nucleation layer is deposited upon Si, Ge/Si, or other single crystal substrate from triethyl gallium (TEG). Deposition from TEG allows a lower deposition temperature which provides a low level of substrate contamination and improved surface morphology.
    Type: Grant
    Filed: November 13, 1987
    Date of Patent: March 20, 1990
    Assignee: Kopin Corporation
    Inventors: Jhang W. Lee, Richard E. McCullough, Jack P. Salerno
  • III-V on Si heterostructure using a thermal strain layer
    Patent number: 4900372
    Abstract: A method for producing wafers having deposited layers of III-V materials on Si or Ge/Si substrates is disclosed. The method involves the use of multiple in situ and ex situ annealing steps and the formation of a thermal strain layer to produce wafers having a decreased incidence of defects and a balanced thermal strain. The wafers produced thereby are also disclosed.
    Type: Grant
    Filed: March 2, 1989
    Date of Patent: February 13, 1990
    Assignee: Kopin Corporation
    Inventors: Jhang W. Lee, Richard E. McCullough
  • Annealing method for III-V deposition
    Patent number: 4835116
    Abstract: A method for producing wafers having deposited layers of III-V materials on Si or Ge/Si substrates is disclosed. The method involves the use of multiple in situ and ex situ annealing steps and the formation of a thermal strain layer to produce wafers having a decreased incidence of defects and a balanced thermal strain. The wafers produced thereby are also disclosed.
    Type: Grant
    Filed: November 13, 1987
    Date of Patent: May 30, 1989
    Assignee: Kopin Corporation
    Inventors: Jhang W. Lee, Richard E. McCullough
  • Selective OMCVD growth of compound semiconductor materials on silicon substrates
    Patent number: 4826784
    Abstract: A method of OMCVD heteroepitaxy of III/V (GaAs) material on a patterned Si substrate is described wherein heteroepitaxy deposition occurs only on the exposed Si surfaces and nowhere else.
    Type: Grant
    Filed: November 13, 1987
    Date of Patent: May 2, 1989
    Assignee: Kopin Corporation
    Inventors: Jack P. Salerno, Jhang W. Lee, Richard E. McCullough