Abstract: Data is promoted from a backing store (disk storage apparatus termed DASD) to a random access cache in a peripheral data storage system. When a sequential access bit is sent to the storage system, all data specified in a read command is fetched to the cache from DASD. If such prefetched data is replaced from cache and the sequential bit is on, a subsequent host access request for such data causes all related data, up to a predetermined maximum, not yet read to be promoted to cache.

Abstract: In a data storage system employing sequential data transfers for blocks of data bytes, an address offset is induced in the addressing mechanism such that each block transfer requires loading the address mechanism with an address of a block to be accessed. Address offset is preferably induced by inserting a blank register between adjacent blocks.

Abstract: A plurality of addressable data storage devices are selectively directly accessed or accessed via a cache memory. Access via the cache memory uses one of a plurality of logical addresses; each of the data storage devices is represented by a plurality of the logical addresses. Each of the data storage devices can be reserved for direct access; such reservation does not apply to device accesses via the cache. Accesses to the devices are queued on a device basis.

Abstract: Direct access storage devices (DASD) are connected to a host via a cache. Each device can be independently addressed by any one of a plurality of addresses, also termed logical devices and exposures. Since operations between DASD and cache are combined for all of the independent logical devices, resetting operations related to one independent logical device can inadvertently interfere with operations of another independent logical device. To maintain data integrity, a programmed control accommodates logical device independence by using queues and control blocks relating to the DASD and logical devices, respectively.