Abstract: An apparatus for integer exception register (XER) renaming and methods of using the same are implemented. In a central processing unit (CPU) having a pipelined architecture, integer instructions that use or update the XER may be executed out-of-order using the XER renaming mechanism. Any instruction that updates the XER has an associated instruction identifier (IID) stored in a register. Subsequent instructions that use data in the XER use the stored IID to determine when the XER data has been updated by the execution of the instruction corresponding to the stored IID. As each instruction that updates XER data is executed, the data is stored in an XER rename buffer. Instructions using XER data then obtain the updated, valid, XER data from the rename buffer. In this way, these instructions can obtain valid XER data prior to completion of the preceding instructions. The XER data is retrieved from the XER rename buffer by indexing into the buffer by using an index derived from the stored IID.

Abstract: A method and system for interchanging operands and loading such operands into a plurality of operand registers in an execution unit with the data processing system during execution of a complex instruction. A plurality of operands are stored within a register file, including a first operand and a second operand. An instruction is loaded into the first stage of the execution pipe within the execution unit, wherein the instruction has a plurality of fields. Such fields include a first and second field, containing a first and second operand pointer, respectively, for designating a value stored in the register file for loading into first and second operand registers, respectively. Next, the first and second operand pointers are interchanged between the first and second fields.