Abstract: Apparatus is disclosed for generating pseudo-random bit patterns that are applied to a data processor, or other digital logic unit, for test purposes. In accordance with the invention, certain of the elemental storage units (e.g., flipflops) of the data processor are designed for two-mode operation: A normal mode of operation during which they operate as a part of the data processor in normal fashion, and a scan mode operation during which the elemental storage units respond to scan control signals to form a number of shift register or scan line configurations for receiving the pseudo-random sequenced or non-random sequenced test patterns generated by the apparatus. During testing, the bit patterns are passed through the scan line configurations and applied to compression circuits where, using cyclic redundancy checking (CRC), compression bit patterns received from the scan lines are achieved.

Abstract: A scannable asynchronous/synchronous CMOS latch circuit that includes a first, second, and third latch element, an asynchronous latch section, and a clock control section. When operated as a synchronous latch, the first latch element operates as the "master" portion and the second latch element acts as the "slave" portion of a master/slave latch. The clock control circuit enables the clock signals to control the synchronous operation of the master/slave latch. When operated as an asynchronous latch, the clock control circuit disables the clock. The output of the asynchronous latch section is connected to the input of the first latch element. An asynchronous signal appearing on one of the inputs of the asynchronous latch section passes through the first and second latch elements and is applied to another input of the asynchronous latch section, causing it to be latched, or held. Separate outputs are provided for the asynchronous latch and the synchronous latch.