Abstract: Devices, systems and/or methods for repairing soft tissue adjacent a repair site. In one embodiment, a repair device is delivered with a delivery device system configured to move a cartridge with the repair device disposed therein toward an anvil with soft tissue positioned thereon. The delivery device linearly moves the cartridge toward the anvil with a worm drive positioned within a housing by rotating a thumb wheel disposed around the worm drive. Such linear movement is provided with a finger element extending from the worm drive that is configured to cooperate with an internal surface of the thumb wheel. With this arrangement, upon rotating the thumb wheel, the worm drive rotates with the finger element engaged with the internal surface of the thumb wheel to linearly move the cartridge toward the anvil.

Abstract: Devices, systems and/or methods for repairing soft tissue adjacent a repair site. In one embodiment, a repair device includes a plate member and an anchor. The plate member having a periphery, the plate member configured to be positioned along an outer surface of the soft tissue. The anchor includes a base and six legs extending from the base, the six legs extending from the base being moveable to a curled configuration such that the six legs wrap around separate portions of the periphery of the plate member with the soft tissue therebetween. In this manner, the repair device may be anchored to the soft tissue.

Abstract: Disclosed is a radio frequency integrated circuit (RFIC) chip that includes an integrated circuit (IC) area and a crackstop laterally surrounding the IC area. The crackstop includes a metallic barrier (or, alternatively, concentric metallic barriers) electrically isolated from the IC area. One or more noise suppressors and, particularly, one or more passive filters (e.g., low pass filter(s), high pass filter(s), band pass filter(s), and/or band stop filter(s)) are integrated into the structure of the metallic barrier(s) to inhibit propagation, through the crackstop, of noise signals within a specific RF range. The specific RF range can be a customer-specified operating parameter. By embedding customized noise suppressor(s) into the crackstop, local signal interference unique to the customer-specified operating parameters can be minimized while also avoiding or at least minimizing the risk of moisture ingress to the IC area. Also disclosed is a method of forming the chip.

Abstract: Disclosed is a radio frequency integrated circuit (RFIC) chip that includes an integrated circuit (IC) area and a crackstop laterally surrounding the IC area. The crackstop includes a metallic barrier (or, alternatively, concentric metallic barriers) electrically isolated from the IC area. One or more noise suppressors and, particularly, one or more passive filters (e.g., low pass filter(s), high pass filter(s), band pass filter(s), and/or band stop filter(s)) are integrated into the structure of the metallic barrier(s) to inhibit propagation, through the crackstop, of noise signals within a specific RF range. The specific RF range can be a customer-specified operating parameter. By embedding customized noise suppressor(s) into the crackstop, local signal interference unique to the customer-specified operating parameters can be minimized while also avoiding or at least minimizing the risk of moisture ingress to the IC area. Also disclosed is a method of forming the chip.

Abstract: Disclosed is a semiconductor structure including a lateral heterojunction bipolar transistor (HBT). The structure includes a substrate (e.g., a silicon substrate), an insulator layer on the substrate, and a semiconductor layer (e.g., a silicon germanium layer) on the insulator layer. The structure includes a lateral HBT with three terminals including a collector, an emitter, and a base, which is positioned laterally between the collector and the emitter and which can include a silicon germanium intrinsic base region for improved performance. Additionally, the collector and/or the emitter includes: a first region, which is epitaxially grown within a trench that extends through the semiconductor layer and the insulator layer to the substrate; and a second region, which is epitaxially grown on the first region. The connection(s) of the collector and/or the emitter to the substrate effectively form thermal exit path(s) and minimize self-heating. Also disclosed is a method for forming the structure.

Abstract: Embodiments of the disclosure provide a bipolar junction transistor (BJT) structure and related method. A BJT according to the disclosure may include a base over a semiconductor substrate. A collector is over the semiconductor substrate and laterally abuts a first horizontal end of the base. An emitter is over the semiconductor substrate and laterally abuts a second horizontal end of the base opposite the first horizontal end. A horizontal interface between the emitter and the base is smaller than a horizontal interface between the collector and the base.

Abstract: Disclosed is a semiconductor structure including at least one bipolar junction transistor (BJT), which is uniquely configured so that fabrication of the BJT can be readily integrated with fabrication of complementary metal oxide semiconductor (CMOS) devices on an advanced silicon-on-insulator (SOI) wafer. The BJT has an emitter, a base, and a collector laid out horizontally across an insulator layer and physically separated. Extension regions extend laterally between the emitter and the base and between the base and the collector and are doped to provide junctions between the emitter and the base and between the base and the collector. Gate structures are on the extension regions. The emitter, base, and collector are contacted. Optionally, the gate structures and a substrate below the insulator layer are contacted and can be biased to optimize BJT performance. Optionally, the structure further includes one or more CMOS devices. Also disclosed is a method of forming the structure.

Abstract: Disclosed is a semiconductor structure that includes an asymmetric lateral bipolar junction transistor (BJT). The BJT includes an emitter, a base, a collector extension and a collector arranged side-by-side (i.e., laterally) across a semiconductor layer. The emitter, collector and collector extension have a first type conductivity with the collector extension having a lower conductivity level than either the emitter or the collector. The base has a second type conductivity that is different from the first type conductivity. With such a lateral configuration, the BJT can be easily integrated with CMOS devices on advanced SOI technology platforms. With such an asymmetric configuration and, particularly, given the inclusion of the collector extension but not an emitter extension, the BJT can achieve a relatively high collector-emitter breakdown voltage (Vbr-CEO) without a significant risk of leakage currents at high voltages. Also disclosed are method embodiments for forming such a semiconductor structure.

Abstract: Disclosed is a radio frequency integrated circuit (RFIC) chip that includes an integrated circuit (IC) area and a crackstop laterally surrounding the IC area. The crackstop includes a metallic barrier (or, alternatively, concentric metallic barriers) electrically isolated from the IC area. One or more noise suppressors and, particularly, one or more passive filters (e.g., low pass filter(s), high pass filter(s), band pass filter(s), and/or band stop filter(s)) are integrated into the structure of the metallic barrier(s) to inhibit propagation, through the crackstop, of noise signals within a specific RF range. The specific RF range can be a customer-specified operating parameter. By embedding customized noise suppressor(s) into the crackstop, local signal interference unique to the customer-specified operating parameters can be minimized while also avoiding or at least minimizing the risk of moisture ingress to the IC area. Also disclosed is a method of forming the chip.

Abstract: Disclosed is a semiconductor structure including at least one bipolar junction transistor (BJT), which is uniquely configured so that fabrication of the BJT can be readily integrated with fabrication of complementary metal oxide semiconductor (CMOS) devices on an advanced silicon-on-insulator (SOI) wafer. The BJT has an emitter, a base, and a collector laid out horizontally across an insulator layer and physically separated. Extension regions extend laterally between the emitter and the base and between the base and the collector and are doped to provide junctions between the emitter and the base and between the base and the collector. Gate structures are on the extension regions. The emitter, base, and collector are contacted. Optionally, the gate structures and a substrate below the insulator layer are contacted and can be biased to optimize BJT performance. Optionally, the structure further includes one or more CMOS devices. Also disclosed is a method of forming the structure.

Abstract: Embodiments of the disclosure provide a bipolar junction transistor (BJT) structure and related method. A BJT according to the disclosure may include a base over a semiconductor substrate. A collector is over the semiconductor substrate and laterally abuts a first horizontal end of the base. An emitter is over the semiconductor substrate and laterally abuts a second horizontal end of the base opposite the first horizontal end. A horizontal interface between the emitter and the base is smaller than a horizontal interface between the collector and the base.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to virtual drains for decreased harmonic generation in fully depleted SOI (FDSOI) RF switches and methods of manufacture. The structure includes one or more active devices on a semiconductor on insulator material which is on top of a substrate; and a virtual drain region composed of a well region within the substrate and spaced apart from an active region of the one or more devices, the virtual drain region configured to be biased to collect electrons which would accumulate in the substrate.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to virtual drains for decreased harmonic generation in fully depleted SOI (FDSOI) RF switches and methods of manufacture. The structure includes one or more active devices on a semiconductor on insulator material which is on top of a substrate; and a virtual drain region composed of a well region within the substrate and spaced apart from an active region of the one or more devices, the virtual drain region configured to be biased to collect electrons which would accumulate in the substrate.

Abstract: A method to attach a V-shaped or parabolic-shaped blast shield or other blast shields, to the bottom of a vehicle space frame that serves the purpose of redirecting the blast forces away from the crew compartment of the vehicle. Inner beams that run the length or width of the blast shield, align with the space frame running in the same direction. The beams are attached with bolts going through the top of each beam and into a threaded boss welded in the space frame. To attach the sides of the blast shield to the space frame, a rail adapter bracket mounts to the bottom of the space frame that has threaded bosses welded into the space frame. Slotted holes for forward and back and side-to-side adjustment on an adapter bracket are employed to help attach the blast shield to the space frame.

Abstract: The accuracy of the width measurement of a semiconductor resistor is improved by modifying the gate mask of a standard MOS transistor fabrication process to form an opening between regions of polysilicon that are used as a mask when the substrate or well material is implanted to form the resistor.

Abstract: A method of immobilizing and stabilizing an active biological receptor in a polymeric film and receptor-based biosensors for determining an analyte of interest in a sample. The receptor-based biosensors include a polymeric film having a biological receptor capable of binding an analyte of interest immobilized therein according to the method of the present invention and an electrical means for determining the presence and quantity of the analyte. In particular, acetylcholine receptor and opiate receptor have been immobilized in a polymeric film made by combining the receptor, a material (e.g., bovine serum albumin, gelatin) capable of polymerizing and a polymerizing agent (e.g., glutaradehyde).

Abstract: An electrical biosensor for analyte determination is prepared by polymerization of a mixture of a biological receptor capable of binding an analyte in a sample, a protein and a polymerizing agent such as glutaraldehyde to form a polymeric film on a transducer. The mixture preferably contains a stabilizer selected from lipids, detergents and antioxidents. The receptor may be an acetylcholine receptor and the analyte, acetylcholine. A preferred stabilizer is a combination of phosphatidyl choline and octyphenoxypolyethoxyethanol. In carrying out a determination, analyte in a sample binds to the receptor causing a change in an electrical characteristic of the film which is indicative of the presence of the analyte. The biosensor may contain a second polymeric film that is free of the receptor and which serves as a control.

Abstract: This invention is conerned with conveyors using reciprocating flights to convey material along the length of the conveyor. The conveyor consists essentially of a bed of articulated plates, a track constraining a chain adjacent a first longitudinal edge of the bed, spaced flights attached to the chain and located to extend across the bed and means for reciprocating the chain along the track. The chain is preferably made of rigid members of substantially uniform cross-section and the flights are shaped bars having one end adapted to be pivotally attached to the chain and are reduced in their height towards their free ends with the trailing edges of each flight tapered downwardly towards their bottom surfaces and inclined towards the leading edges at their free ends which ends are chamfered.