Abstract: Systems and methods for positioning an output element (102, 602) within a three-dimensional environment (104, 604) are described. Movement data relating to movement of a mobile device (120, 620) is obtained (206, 262). The movement data is mapped (208, 264) to movement of a simulated output element (503) in a virtual environment (505), which simulates the three-dimensional environment. The movement of the simulated output element is associated with movement of an output element within the three-dimensional environment so as to control the position of the output element within the three-dimensional environment. In one exemplary embodiment an output element (102) being a sound source is positioned in a three-dimensional, immersive sound environment (104). In another exemplary embodiment a focal point of a light beam (602) is positioned in a three-dimensional theatrical environment (604).

Abstract: Systems and methods for positioning an output element (102, 602) within a three-dimensional environment (104, 604) are described. Movement data relating to movement of a mobile device (120, 620) is obtained (206, 262). The movement data is mapped (208, 264) to movement of a simulated output element (503) in a virtual environment (505), which simulates the three-dimensional environment. The movement of the simulated output element is associated with movement of an output element within the three-dimensional environment so as to control the position of the output element within the three-dimensional environment. In one exemplary embodiment an output element (102) being a sound source is positioned in a three-dimensional, immersive sound environment (104). In another exemplary embodiment a focal point of a light beam (602) is positioned in a three-dimensional theatrical environment (604).

Abstract: An apparatus for modifying a command message (CMD) received from a source apparatus to control a target device parameter of a target apparatus within a digital multimedia network, wherein a hierarchical parameter address (HPA) or a parameter value contained in said command message (CMD) is changed according to at least one change script to provide a modified command message (CMD?).

Abstract: A digital multimedia network with a parameter join mechanism comprising at least one apparatus. A requesting device parameter of a source apparatus updates a local parameter group list by adding an entry for each device parameter of a target apparatus which joins the parameter group.

Abstract: The present invention concerns a router for providing isochronous data transfer and asynchronous data transfer on the basis of a predetermined protocol between devices of different network sections connected to the router, when a connection management application executed by the router translates a user request to transfer data from a transmitting device of a first network section to a receiving device of a second network section into commands of the protocol for establishing a first data connection between the transmitting device and the router and a second data connection between the router and the receiving device when the data is transferred from the transmitting device via the established data connections to the receiving device.

Abstract: The present invention relates to a digital multimedia network 1 with latency control comprising apparatuses for processing of data streams, wherein a borderline input apparatus providing a data stream generates a latency time stamp (LTS) which contains an absolute time indicating a creation time of said data stream and an accumulated delay time which is updated by each apparatus processing said data stream, wherein said latency time stamp (LTS) of said data stream is evaluated by a borderline output apparatus of said network which synchronizes said data stream.

Abstract: The present invention relates to a digital multimedia network with a parameter join mechanism comprising at least one apparatus, wherein a requesting device parameter of a source apparatus updates a local parameter group list (PGL) by adding an entry for each device parameter of a target apparatus which joins said parameter group (PG).

Abstract: An apparatus for modifying a command message (CMD) received from a source apparatus to control a target device parameter of a target apparatus within a digital multimedia network, wherein a hierarchical parameter address (HPA) or a parameter value contained in said command message (CMD) is changed according to at least one change script to provide a modified command message (CMD').

Abstract: The present invention relates to a digital multimedia network of apparatuses each comprising a control device, wherein a device parameter of an apparatus is controlled by sending a command message (CMD) to said control device of said apparatus containing a tree-structured hierarchical parameter address (HPA) which consists of parameter grouping identifiers each corresponding to a hierarchy level of a predetermined tree-structured parameter hierarchy used for addressing device parameters throughout said digital multimedia network.

Abstract: The present invention relates to a digital multimedia network 1 with latency control comprising apparatuses for processing of data streams, wherein a borderline input apparatus providing a data stream generates a latency time stamp (LTS) which contains an absolute time indicating a creation time of said data stream and an accumulated delay time which is updated by each apparatus processing said data stream, wherein said latency time stamp (LTS) of said data stream is evaluated by a borderline output apparatus of said network which synchronizes said data stream.

Abstract: The invention provides a router for providing isochronous data transfer and asynchronous data transfer on the basis of a predetermined protocol between devices of different network sections connected to said router, wherein a connection management application executed by said router translates a user request to transfer data from a transmitting device of a first network section to a receiving device of a second network section into commands of said protocol for establishing a first data connection between said transmitting device and said router and a second data connection between said router and said receiving device, wherein said data is transferred from said transmitting device via the established data connections to said receiving device.

Abstract: The invention provides a desktop control and a browser for a host apparatus of a digital multimedia network. The desktop control comprises a processing core having at least one desk parameter link (DPL) to a device parameter of the host apparatus. Furthermore, the processing core can have at least one desk application link (DAL) to a browser application of the host apparatus. The processing core further has one or more desk item links to other desktop controls of another apparatus within the digital multimedia network.

Abstract: An embedded DRAM ECC architecture for purging data errors. The embedded DRAM ECC architecture is based upon a two-dimensional linear parity scheme, and includes a plurality of memory blocks and a parity block. Each memory block includes additional columns for storing row parity bits, and the parity block stores column parity bits. A row parity circuit coupled in parallel to an existing local databus of each memory checks the parity of the local databus bits against a row parity bit during a refresh or read operation to identify parity failure. Identification of the incorrect bit of the word is achieved by iteratively transferring the data of the local databus of each memory block onto an existing global databus, and checking the parity across the global databus with a column parity circuit. When global databus parity failure is detected, all bits of the global databus are inverted to purge the incorrect bit from the memory block via the local databus.

Abstract: A method and circuit is provided for detecting and correcting errors in an array of content addressable memory (CAM) cells. The array includes wordlines, searchlines, bitlines, and matchlines for reading from, writing to, and searching CAM cells in the array.

Abstract: An embedded DRAM ECC architecture for purging data errors. The embedded DRAM ECC architecture is based upon a two-dimensional linear parity scheme, and includes a plurality of memory blocks and a parity block. Each memory block includes additional columns for storing row parity bits, and the parity block stores column parity bits. A row parity circuit coupled in parallel to an existing local databus of each memory checks the parity of the local databus bits against a row parity bit during a refresh or read operation to identify parity failure. Identification of the incorrect bit of the word is achieved by iteratively transferring the data of the local databus of each memory block onto an existing global databus, and checking the parity across the global databus with a column parity circuit. When global databus parity failure is detected, all bits of the global databus are inverted to purge the incorrect bit from the memory block via the local databus.

Abstract: An embedded DRAM ECC architecture for purging data errors. The embedded DRAM ECC architecture is based upon a two-dimensional linear parity scheme, and includes a plurality of memory blocks and a parity block. Each memory block includes additional columns for storing row parity bits, and the parity block stores column parity bits. A row parity circuit coupled in parallel to an existing local databus of each memory checks the parity of the local databus bits against a row parity bit during a refresh or read operation to identify parity failure. Identification of the incorrect bit of the word is achieved by iteratively transferring the data of the local databus of each memory block onto an existing global databus, and checking the parity across the global databus with a column parity circuit. When global databus parity failure is detected, all bits of the global databus are inverted to purge the incorrect bit from the memory block via the local databus.

Abstract: A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2Vdd. Transistors in a boosting circuit are fully switched, eliminating reduction of the boosting voltage by Vtn through the transistors. The boosting capacitors are charge by Vdd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.

Abstract: A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers being connected in a two dimensional array, pairs of primary databuses being connected through first access transistors to plural corresponding bit line sense amplifiers in each row of the array, apparatus for enabling columns of the first access transistors, databus sense amplifiers each connected to a corresponding data bus pair, a secondary databus, the secondary databus being connected through second access transistors to the databus sense amplifiers, and apparatus for enabling the second access transistors, whereby each the primary databus pair may be shared by plural sense amplifiers in a corresponding row of the array and the secondary databus may be shared by plural primary databus pairs.

Abstract: A method and circuit is provided for detecting and correcting errors in an array of content addressable memory (CAM) cells. The array includes wordlines, searchlines, bitlines, and matchlines for reading from, writing to, and searching CAM cells in the array.

Abstract: A method and circuit is provided for detecting and correcting errors in an array of content addressable memory (CAM) cells. The array includes wordlines, searchlines, bitlines, and matchlines for reading from, writing to, and searching CAM cells in the array.