Abstract: A method and system enable cross connection of an incoming data stream to one or more outgoing data streams. Each data stream comprises respective incoming and outgoing frames. Each frame includes one or more rows, and each row comprises a respective plurality of data segments. A reserved memory space is provided having a data storage capacity equal to an integer multiple of a data segment and less than one complete row. A data segment of an incoming row of an incoming frame is written to the reserved memory space. Subsequently, the data segment of the incoming row is read to an outgoing row of an outgoing frame from the reserved memory space. The writing and reading steps are timed such that the data segment is read from the reserved memory space before being over-written by another data segment.

Abstract: The present invention is directed to a shelf for housing PCPs. A backplane extends across the shelf. A connector module having the OAM&P connectors is electrically connected to the backplane and has two positions. In one position it extends sideways from the shelf with the connectors in a front to rear direction. In the second position, the OAM&P connector module is substantially flush with the side of the shelf.

Abstract: A shelf for housing printed circuit packs in which a backplane has a connector along its top or bottom edge. Connector modules are connected to the backplane by vertical attachment to the backplane edge connector such that the connector modules are located above or below the backplane. The connector modules may be oriented either to be front facing or rear facing. The backplane connector is adapted to accept modules of varying widths and having different connectors thereon.

Abstract: An apparatus is provided for delaying digital data signals by fixed amounts within an integrated circuit. A delay lock loop includes an adaptive delay line, a phase detector and an integrator. The integrator provides control signals c.sub.p, c.sub.n for controlling the delay line, in dependence upon the relative phase of a reference clock signal .phi..sub.0 and a delayed clock signal .phi..sub.n. The delay line includes a plurality of delay cells. By maintaining a phase relationship .phi..sub.n =.phi..sub.0 +360.degree. one clock cycle, T.sub.c, delay through the delay line is provided. Thus each delay cell provides T.sub.c /n delay. By placing identical cells in signal paths elsewhere on a chip, fixed delays can be introduced which are controlled by the delay lock loop. A harmonic lock detector connected to a plurality of clock phase taps from the delay line detects harmonic lock conditions for second through tenth harmonics, resetting the delay lock loop in the event of harmonic lock.

Abstract: An apparatus is provided for delaying digital data signals by fixed amounts within an integrated circuit. A delay lock loop includes an adaptive delay line, a phase detector and an integrator. The integrator provides control signals c.sub.p, c.sub.n for controlling the delay line, in dependence upon the relative phase of a reference clock signal .phi..sub.0 and a delayed clock signal .phi..sub.n. The delay line includes a plurality of delay cells. By maintaining a phase relationship .phi..sub.n =.phi..sub.0 +360.degree. one clock cycle, T.sub.c, delay through the delay line is provided. Thus each delay cell provides T.sub.c /n delay. By placing identical cells in signal paths elsewhere on a chip, fixed delays can be introduced which are controlled by the delay lock loop.