Patents by Inventor Richard G. Southwick

Richard G. Southwick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dual channel silicon/silicon germanium complementary metal oxide semiconductor performance with interface engineering
    Patent number: 10790199
    Abstract: A method of forming fin structures that includes providing at least one silicon germanium containing fin structure, and forming a fin liner on the at least one silicon germanium containing fin structure. The fin liner includes a silicon germanium and oxygen containing layer. The method continues with annealing the at least on silicon germanium containing fin structure having the fin liner present thereon. During the annealing, the silicon germanium oxygen containing layer reacts with the silicon germanium containing fin structure to provide surface formation of a silicon rich layer on the silicon germanium containing fin structure.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: September 29, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Ruqiang Bao, Hemanth Jagannathan, Choonghyun Lee, Richard G. Southwick
  • Simplified gate stack process to improve dual channel CMOS performance
    Patent number: 10395079
    Abstract: A semiconductor device and method of making the same wherein the semiconductor device includes a pFET region including a SiGe channel having a Si-rich top surface within the gate portion, and an nFET region including a Si channel. The method includes subjecting both the pFET and nFET regions to a single high-temperature anneal process thereby avoiding the need for an additional spike anneal process at RMG module.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hemanth Jagannathan, ChoongHyun Lee, Richard G. Southwick, III
  • Simplified gate stack process to improve dual channel CMOS performance
    Patent number: 10395080
    Abstract: A semiconductor device and method of making the same wherein the semiconductor device includes a pFET region including a SiGe channel having a Si-rich top surface within the gate portion, and an nFET region including a Si channel. The method includes subjecting both the pFET and nFET regions to a single high-temperature anneal process thereby avoiding the need for an additional spike anneal process at RMG module.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hemanth Jagannathan, ChoongHyun Lee, Richard G. Southwick, III
  • DUAL CHANNEL SILICON/SILICON GERMANIUM COMPLEMENTARY METAL OXIDE SEMICONDUCTOR PERFORMANCE WITH INTERFACE ENGINEERING
    Publication number: 20190229020
    Abstract: A method of forming fin structures that includes providing at least one silicon germanium containing fin structure, and forming a fin liner on the at least one silicon germanium containing fin structure. The fin liner includes a silicon germanium and oxygen containing layer. The method continues with annealing the at least on silicon germanium containing fin structure having the fin liner present thereon. During the annealing, the silicon germanium oxygen containing layer reacts with the silicon germanium containing fin structure to provide surface formation of a silicon rich layer on the silicon germanium containing fin structure.
    Type: Application
    Filed: April 1, 2019
    Publication date: July 25, 2019
    Inventors: Ruqiang Bao, Hemanth Jagannathan, Choonghyun Lee, Richard G. Southwick
  • Dual channel silicon/silicon germanium complementary metal oxide semiconductor performance with interface engineering
    Patent number: 10361130
    Abstract: A method of forming fin structures that includes providing at least one silicon germanium containing fin structure, and forming a fin liner on the at least one silicon germanium containing fin structure. The fin liner includes a silicon germanium and oxygen containing layer. The method continues with annealing the at least on silicon germanium containing fin structure having the fin liner present thereon. During the annealing, the silicon germanium oxygen containing layer reacts with the silicon germanium containing fin structure to provide surface formation of a silicon rich layer on the silicon germanium containing fin structure.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: July 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Hemanth Jagannathan, Choonghyun Lee, Richard G. Southwick
  • DUAL CHANNEL SILICON/SILICON GERMANIUM COMPLEMENTARY METAL OXIDE SEMICONDUCTOR PERFORMANCE WITH INTERFACE ENGINEERING
    Publication number: 20180315663
    Abstract: A method of forming fin structures that includes providing at least one silicon germanium containing fin structure, and forming a fin liner on the at least one silicon germanium containing fin structure. The fin liner includes a silicon germanium and oxygen containing layer. The method continues with annealing the at least on silicon germanium containing fin structure having the fin liner present thereon. During the annealing, the silicon germanium oxygen containing layer reacts with the silicon germanium containing fin structure to provide surface formation of a silicon rich layer on the silicon germanium containing fin structure.
    Type: Application
    Filed: April 26, 2017
    Publication date: November 1, 2018
    Inventors: Ruqiang Bao, Hemanth Jagannathan, Choonghyun Lee, Richard G. Southwick
  • SIMPLIFIED GATE STACK PROCESS TO IMPROVE DUAL CHANNEL CMOS PERFORMANCE
    Publication number: 20180247096
    Abstract: A semiconductor device and method of making the same wherein the semiconductor device includes a pFET region including a SiGe channel having a Si-rich top surface within the gate portion, and an nFET region including a Si channel. The method includes subjecting both the pFET and nFET regions to a single high-temperature anneal process thereby avoiding the need for an additional spike anneal process at RMG module.
    Type: Application
    Filed: April 20, 2018
    Publication date: August 30, 2018
    Inventors: Hemanth Jagannathan, ChoongHyun Lee, Richard G. Southwick, III
  • SIMPLIFIED GATE STACK PROCESS TO IMPROVE DUAL CHANNEL CMOS PERFORMANCE
    Publication number: 20180247097
    Abstract: A semiconductor device and method of making the same wherein the semiconductor device includes a pFET region including a SiGe channel having a Si-rich top surface within the gate portion, and an nFET region including a Si channel. The method includes subjecting both the pFET and nFET regions to a single high-temperature anneal process thereby avoiding the need for an additional spike anneal process at RMG module.
    Type: Application
    Filed: April 20, 2018
    Publication date: August 30, 2018
    Inventors: Hemanth Jagannathan, ChoongHyun Lee, Richard G. Southwick, III
  • Simplified gate stack process to improve dual channel CMOS performance
    Patent number: 9984263
    Abstract: A semiconductor device and method of making the same wherein the semiconductor device includes a pFET region including a SiGe channel having a Si-rich top surface within the gate portion, and an nFET region including a Si channel. The method includes subjecting both the pFET and nFET regions to a single high-temperature anneal process thereby avoiding the need for an additional spike anneal process at RMG module.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: May 29, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hemanth Jagannathan, ChoongHyun Lee, Richard G. Southwick, III
  • SIMPLIFIED GATE STACK PROCESS TO IMPROVE DUAL CHANNEL CMOS PERFORMANCE
    Publication number: 20180089479
    Abstract: A semiconductor device and method of making the same wherein the semiconductor device includes a pFET region including a SiGe channel having a Si-rich top surface within the gate portion, and an nFET region including a Si channel. The method includes subjecting both the pFET and nFET regions to a single high-temperature anneal process thereby avoiding the need for an additional spike anneal process at RMG module.
    Type: Application
    Filed: May 24, 2017
    Publication date: March 29, 2018
    Inventors: Hemanth Jagannathan, ChoongHyun Lee, Richard G. Southwick, III
  • Simplified gate stack process to improve dual channel CMOS performance
    Patent number: 9741822
    Abstract: A semiconductor device and method of making the same wherein the semiconductor device includes a pFET region including a SiGe channel having a Si-rich top surface within the gate portion, and an nFET region including a Si channel. The method includes subjecting both the pFET and nFET regions to a single high-temperature anneal process thereby avoiding the need for an additional spike anneal process at RMG module.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: August 22, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hemanth Jagannathan, ChoongHyun Lee, Richard G. Southwick, III