Abstract: A data storage device includes a memory device including a plurality of wordlines, each wordline having a plurality of cells, and a cell statistics generator (CSG) disposed on the memory device. The CSG includes logic configured to receive a plurality of left read senses and a plurality of right read senses for the plurality of cells of a wordline, determine a plurality of first windows and a plurality of second windows, determine a left window sum and a right window sum, determine a deviation parameter and a dispersion parameter based on the left window sum and the right window sum, and determine one or more characteristics of the plurality of cells based on the deviation parameter and the dispersion parameter. The deviation parameter and the dispersion parameter are used to describe a number of errors of the left read sense and the right read sense.

Abstract: Example systems, read channels, and methods provide an oversampled digital phase lock loop for use in a read channel. The phase lock loop receives a digital data signal comprised of oversampled digital signal values with a sample rate that is a multiple of the baud rate of the channel. A set of oversampled digital signal values is selected for each iteration of the phase lock loop to correct the phase of an analog-to-digital converter. The phase lock loop determines a phase gradient, based on an iterative detector, and feeds back a phase correction for the next iteration of the phase lock loop. A baud rate digital data signal is provided to the rest of the channel based on down sampling or interpolated based on the phase gradient.

Abstract: Example systems, read channels, and methods provide an oversampled digital phase lock loop for use in a read channel. The phase lock loop receives a digital data signal comprised of oversampled digital signal values with a sample rate that is a multiple of the baud rate of the channel. A set of oversampled digital signal values is selected for each iteration of the phase lock loop to correct the phase of an analog-to-digital converter. The phase lock loop determines a phase gradient, based on an iterative detector, and feeds back a phase correction for the next iteration of the phase lock loop. A baud rate digital data signal is provided to the rest of the channel based on down sampling or interpolated based on the phase gradient.

Abstract: Example systems, read channels, and methods provide states equalization for a digital data signal in preparation for a soft output detector. The states equalizer determines a set of signal values from the digital data signal and filters the set of signal values through a set of finite impulse response filters configured to generate a set of state values for a target signal value, where each filter corresponds to a potential state of the target signal value. Based on the state values, a set of probabilities for possible states is determined and used to populate a decision matrix for a soft output detector.

Abstract: Example control circuitry, data storage devices, and methods to provide a spiral data track format that is different from the underlying servo track format are described. The data storage device may include a storage medium configured with a plurality of tracks in at least one continuous spiral pattern and a head actuated over the storage medium. The data tracks may be written to the storage medium with track lengths that are different than a single revolution of the storage medium.

Abstract: Example channel circuits, data storage devices, and methods for using an adjustable code rate based on an extendable parity code matrix based on write verification determining extended parity are described. A data unit with a base set of parity bits may be written to a non-volatile storage medium and then read back for write verification. The data unit may be decoded using the base set of parity bits and corresponding primary parity matrix. Based on the decoding of the write verification read signal, a number of parity bits for an extended set of parity bits may be determined and the extended set of parity bits may be stored to an extended parity storage location for use during subsequent read operations.

Abstract: Example channel circuits, data storage devices, and methods for asynchronous sampling from an oversampled analog-to-digital converter are described. The channel circuit may include an analog-to-digital converter configured to generate an oversampled digital signal from an analog data signal using a sample rate that is an integer multiple of the baud rate of the channel circuit. A digital sample interpolator may then interpolate interpolated digital signal values from multiple signal values of the oversampled digital signal and select values at baud rate to generate a baud rate digital signal. The baud rate digital signal may be used by an iterative detector in a timing loop and, once a target timing is achieved, for the iterative detector to detect data bits from the interpolated digital signal.

Abstract: Example systems, read channels, and methods provide states equalization for a digital data signal in preparation for a soft output detector. The states equalizer determines a set of signal values from the digital data signal and filters the set of signal values through a set of finite impulse response filters configured to generate a set of state values for a target signal value, where each filter corresponds to a potential state of the target signal value. Based on the state values, a set of probabilities for possible states is determined and used to populate a decision matrix for a soft output detector.

Abstract: Example read channel circuits, data storage devices, and methods to provide overlapping processing of data tracks are described. The data storage device may include media configured with a plurality of tracks in a concentric or continuous pattern. The read signal for a data track may be processed using error correction codes (ECC) as it is read during a first track read operation period. Some portion of its data sectors may need additional ECC postprocessing after the first track is initially received and processed by the read channel circuit. While the read signal for a next data track is being read and processed, the read channel circuit may continue postprocessing of the portion of data sectors from the first track during the second track read operations. Various decision parameters for managing the data stream, additional postprocessing time, and rereading tracks for data recovery are also described.

Abstract: A non-volatile memory device includes a plurality of wordlines, each comprising a plurality of cells, a hard decode configured to read each cell of the plurality of cells at a hard decode voltage, a left read sense configured to read voltage values of each cell to the left of the hard decode voltage at a left read sense voltage, a right read sense configured to read voltage values of each cell to the right of the hard decode voltage at a right read sense voltage, a first combiner configured to determine a difference of voltage values read by the left read sense and right read sense to produce a dispersion signal, and a second combiner configured to determine a sum of the voltage values read by the left read sense and right read sense to produce a deviation signal.

Abstract: Example control circuitry, data storage devices, and methods to provide a spiral data track format that is different from the underlying servo track format are described. The data storage device may include a storage medium configured with a plurality of tracks in at least one continuous spiral pattern and a head actuated over the storage medium. The data tracks may be written to the storage medium with track lengths that are different than a single revolution of the storage medium.

Abstract: Example channel circuits, data storage devices, and methods for using an adjustable code rate based on an extendable parity code matrix are described. Data units may be read from a storage medium. Multiple sets of parity bits may be available for different data units, different sets of parity bits having a different number of parity bits corresponding to different parity matrices and desired code rates. A primary parity matrix may provide a base code rate and one or more extended parity matrices may provide increased code rates based on additional rows for increased decoding. Error correction code (ECC) decoding may be selectively performed based on the different sets of parity bits and corresponding parity matrices, resulting in the output of a decoded data units based on the data units from the read signal.

Abstract: Example systems, read channels, and methods provide bit value detection from an encoded data signal using a neural network soft information detector. The neural network detector determines a set of probabilities for possible states of a data symbol from the encoded data signal. A soft output detector uses the set of probabilities for possible states of the data symbol to determine a set of bit probabilities that are iteratively exchanged as extrinsic information with an iterative decoder for making decoding decisions. The iterative decoder outputs decoded bit values for a data unit that includes the data symbol.

Abstract: Example read channel circuits, data storage devices, and methods to provide overlapping processing of data tracks are described. The data storage device may include media configured with a plurality of tracks in a concentric or continuous pattern. The read signal for a data track may be processed using error correction codes (ECC) as it is read during a first track read operation period. Some portion of its data sectors may need additional ECC postprocessing after the first track is initially received and processed by the read channel circuit. While the read signal for a next data track is being read and processed, the read channel circuit may continue postprocessing of the portion of data sectors from the first track during the second track read operations. Various decision parameters for managing the data stream, additional postprocessing time, and rereading tracks for data recovery are also described.

Abstract: Example channel circuits, data storage devices, and methods for using an extendable parity code matrix are described. A data unit may be read from a storage medium. Multiple sets of parity bits may be available for the data unit, each set of parity bits having a different number of parity bits corresponding to different parity matrices, including a primary parity matrix and at least one extended parity matrix. The extended parity matrix includes the primary parity matrix and additional rows for increased decoding. Error correction code (ECC) decoding may be selectively performed based on the different sets of parity bits and corresponding parity matrices, resulting in the output of a decoded data unit based on the data unit from the read signal.

Abstract: Example systems, read channel circuits, data storage devices, and methods to provide signal correction based on soft information in a read channel are described. The read channel circuit includes a soft output detector, such as a soft output Viterbi algorithm (SOVA) detector, and a signal correction circuit. The soft output detector passes detected data bits and corresponding soft information to the signal correction circuit. The signal correction circuit uses the soft information to determine a signal correction value, which is combined with input signal to return a corrected signal to the soft output detector for a next iteration. In some configurations, the signal correction value may compensate for DC offset, AC coupling poles, and/or signal asymmetries to reduce baseline wander in the read channel.

Abstract: Example systems, read channel circuits, data storage devices, and methods to provide signal correction based on soft information in a read channel are described. The read channel circuit includes a soft output detector, such as a soft output Viterbi algorithm (SOVA) detector, and a signal correction circuit. The soft output detector passes detected data bits and corresponding soft information to the signal correction circuit. The signal correction circuit uses the soft information to determine a signal correction value, which is combined with input signal to return a corrected signal to the soft output detector for a next iteration. In some configurations, the signal correction value may compensate for DC offset, AC coupling poles, and/or signal asymmetries to reduce baseline wander in the read channel.

Abstract: Example systems, read channel circuits, data storage devices, and methods to use inter-symbol interference message passing (ISI-MP) data in a read channel are described. The read channel circuit includes a soft output detector, such as a soft output Viterbi algorithm (SOVA) detector, configured to determine both the first most likely and second most likely sets of symbols and output inter-symbol interference data based on the adjacent symbols and corresponding ISI in each set of symbols. The inter-symbol interference data may be used by an ISI-MP circuit configured to model ISI-MP and provide feedback to an iterative decoder during local iterations.

Abstract: A data storage device includes a memory device including a plurality of wordlines, each including a plurality of cells, and a cell statistics generator (CSG) disposed on the memory device. The CSG includes logic configured to receive a first read sense at a threshold voltage of one or more threshold voltages of each cell of a wordline of the plurality of wordlines, determine that a second read sense is required based on the first read sense, receive the second read sense, determine a deviation parameter and a dispersion parameter for an asymmetric adjustment of the left threshold voltage and the right threshold voltage, and adjust the left threshold voltage and the right threshold voltage based on the deviation parameter and the dispersion parameter. The second read sense includes a plurality of left read senses at a left threshold voltage and a plurality of right senses at a right threshold voltage.

Abstract: A data storage device includes a memory device including a plurality of wordlines, each wordline having a plurality of cells, and a cell statistics generator (CSG) disposed on the memory device. The CSG includes logic configured to receive a plurality of left read senses and a plurality of right read senses for the plurality of cells of a wordline, determine a plurality of first windows and a plurality of second windows, determine a left window sum and a right window sum, determine a deviation parameter and a dispersion parameter based on the left window sum and the right window sum, and determine one or more characteristics of the plurality of cells based on the deviation parameter and the dispersion parameter. The deviation parameter and the dispersion parameter are used to describe a number of errors of the left read sense and the right read sense.