Abstract: A system or method to partition data in a memory based at least in part to a data type, and to refresh the memory based at least in part to the data type.

Abstract: A system or method to partition data in a memory based at least in part to a data type, and to refresh the memory based at least in part to the data type.

Abstract: A system or method to partition data in a memory based at least in part to a data type, and to refresh the memory based at least in part to the data type. The claimed subject matter relates to organizing data in a memory for a refresh operation.

Abstract: A system and method to adjust a voltage level to a processor based at least in part on the system's temperature and/or clock frequency.

Abstract: A system or memory to support an adjustable frequency of a memory based at least in part on the sensed temperature of the memory.

Abstract: A system or method to partition data in a memory based at least in part to a data type, and to refresh the memory based at least in part to the data type.

Abstract: A hard-wired circuit for sorting data including an input for receiving a new multibit word of a series of multibit words to be sorted, a plurality of comparators and respective storage devices, each comparator being connected to receive a sorted multibit word stored in its associated storage device and the new multibit word from the input and to compare the multibit words simultaneously with comparisons of other comparators and to provide a comparison output, and a controller responsive to the comparison outputs to store the new multibit word at a storage device such that it is in proper position with respect to sorted multibit words stored in other storage devices.

Abstract: An image decoding apparatus including a Huffman decoder for decoding CCITT-encoded image information encoded in both one-dimensional and two-dimensional encoding to sequentially generate individual symbols each associated with a pixel run. A relative address decoder receives each symbol from the Huffman decoder and generates, in response thereto, an item of run length information and a color value representing the color of the pixel run. Finally, a run length decoder sequentially receives the successive items of run length information and uses them in generating sequential words for transmission to, for example, a display device. The run-length decoder iteratively receives run-length information comprising a length value and a data value and generates in response thereto a series of fixed-length data words of predetermined length. The run-length decoding apparatus includes a run pointer control circuit and a data word creator circuit.