Abstract: A data processing system with a microprocessor that has an instruction execution pipeline that includes fetch and decode stages and several functional execution units. Fetch packets contain a plurality of instruction words. Execution packets include a plurality of instruction words that can be executed in parallel by two or more execution units. An execution packet can span two or more fetch packets. An add (k) constant to program counter (ADDKPC) instruction is provided, such that a parameter specified by the ADDKPC instruction is combined with a value provided by a program counter of microprocessor. The ADDKPC instruction can also specify a number of delay slots after a branch instruction to be filled with virtual NOP instructions such that memory is not wasted with useless NOP instructions. An ADDKPC instruction can provide a relative address for use as a return address. A plurality of predicated ADDKPC instructions can provide a return address selected from a plurality of return addresses.

Abstract: A data processing system is provided with a digital signal processor which has an instruction for shifting a source operand in response to a signed shift count value and storing the shifted result in a selected destination register. A first 32-bit operand (600) is treated as a signed shift value that has a sign and a shift count value. A second operand (602) is shifted by an amount according to the shift count value and in a direction according to the sign of the shift count. One instruction is provided that performs a right shift for a positive shift count and a left shift for a negative shift count, and another instruction is provided performs a left shift for a positive shift count and a right shift for a negative shift count. If the shift count value is greater than 31, then the shift is limited to 31.

Abstract: A microprocessor and method for operating this microprocessor are disclosed. The microprocessor contains multiple execution units that receive instructions from an instruction pipeline. A loop cache memory is connected in communication with the instruction pipeline, such that it may both store instructions from the instruction pipeline and issue instructions to be executed by the execution units. A loop cache controller controls instruction flow. In operation, the loop cache controller is preferably signaled by a software instruction to begin building a software pipelined loop of a specified size into the loop cache memory. The loop cache controller then begins accumulating instructions from the instruction pipeline into the loop cache memory; these instructions may also remain in the pipeline for execution. When the kernel of the software pipelined loop is built into the loop cache memory, the controller preferably stalls the instruction pipeline and executes the loop using the cached instructions.

Abstract: A microprocessor and method for operating this microprocessor are disclosed. The microprocessor contains multiple execution units that receive instructions from an instruction pipeline. A loop cache memory is connected in communication with the instruction pipeline, such that it may both store instructions from the instruction pipeline and issue instructions to be executed by the execution units. A loop cache controller controls instruction flow.

Abstract: A method of operating a multiple execution unit microprocessor in a software pipelined loop is disclosed. This method executes the loop body before the pipeline is fully initialized, thus replacing prolog instructions with additional loop iterations. The method has the potential to greatly reduce prolog size for many software pipelined loops. As a further aspect of the method, the loop results are insulated from any deleterious effects of loop body execution prior to full initialization—methods for accomplishing this are disclosed, including array overallocation, conditional execution of some loop body instructions, and register initialization.

Abstract: A microprocessor, comprising a first set of functional units capable of performing parallel data operations, a second set of functional units capable of performing parallel data operations, and a data interconnection path connecting the first and second functional units.

Abstract: A method of operating a multiple execution unit microprocessor in a software pipelined loop is disclosed. This method allows the microprocessor to respond to interrupt requests and other runtime conditions during execution of a software pipelined loop utilizing multiple assignment of registers. In one embodiment, the method comprises branching out of the software pipelined loop, upon occurrence of an interrupt request, to an interrupt epilog that consumes in-flight register values and sets the interrupt return pointer to the address of an interrupt prolog. The interrupt is then taken. The interrupt prolog is a subset of the loop prolog, and restores the processor to an operational state equivalent to one that would have existed had the interrupt not been taken. Loop execution is then resumed without data loss or corruption.

Abstract: A microprocessor 1 has an instruction fetch/decode unit 10a-c, a plurality of execution units, including an arithmetic and load/store unit D1, a multiplier M1, an ALU/shifter unit S1, an arithmetic logic unit ("ALU") L1, a shared multiport register file 20a from which data are read and to which data are written, and a memory 22. The microprocessor can execute an instruction which shifts a source operand a specified number of bits and saturates the result if a numerical overflow would result from the shift. Execution unit S1 has circuitry for saturating a destination operand by setting all bits within the destination to represent a most positive or a most negative number in a same single instruction execution phase in which the shift would have occurred if not for the overflow. The saturation circuitry examines the source operand prior to shifting to determine if the destination should be saturated.

Abstract: A microprocessor 1 has an instruction fetch/decode unit 10a-c, a plurality of execution units, including an arithmetic and load/store unit D1, a multiplier M1, an ALU/shifter unit S1, an arithmetic logic unit ("ALU") L1, a shared multiport register file 20a from which data are read and to which data are written, and a memory 22. Execution unit M1 has circuitry for multiplying two operands, shifting the resulting product and saturating the product if an overflow is detected in two execution phase of an instruction execution pipeline.

Abstract: A method for selecting a set of four target bearings from a plurality of bearing measurements to optimize rapidity, accuracy and stability of a target track solution in a bearings-only target motion algorithm. Four bearings are selected to generate the deterministic solution by first selecting a candidate bearing set, then computing a set of "n" solutions from the candidate set and others adjacent thereto. Motion parameters are then computed, and any solution exhibiting parameters outside a user defined deviation from the mean is discarded. The mean target parameters of the remaining solutions may again be computed, and further culling out performed, until the desired distribution is achieved. An optimal solution is chosen as the solution from the remaining sample space that is closest to the mean in target range, course and speed.