Patents by Inventor Richard Hankins

Richard Hankins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8887174
    Abstract: A technique to monitor software thread performance and update software that issues or uses the thread(s) to reduce performance-inhibiting events. At least one embodiment of the invention uses hardware and/or software timers or counters to monitor various events associated with executing user-level threads and report these events back to a user-level software program, which can use the information to avoid or at least reduce performance-inhibiting events associated with the user-level threads.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: November 11, 2014
    Assignee: Intel Corporation
    Inventors: Richard A. Hankins, Gautham N. Chinya, Hong Wang, Shivnandan D. Kaushik, Bryant E. Bigbee, John P. Shen, Trung A. Diep, Xiang Zou, Baiju V. Patel, Paul M. Petersen, Sanjiv M. Shah, Ryan N. Rakvic, Prashant Sethi
  • Patent number: 8839258
    Abstract: A first execution time of a first thread executing on a first processing unit of a multiprocessor is determined. A second execution time of a second thread executing on a second processing unit of the multiprocessor is determined, the first and second threads executing in parallel. Power is set to the first and second processing units to effectuate the first and second threads to finish executing at approximately the same time in future executions of the first and second threads. Other embodiments are also described and claimed.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: September 16, 2014
    Assignee: Intel Corporation
    Inventors: Ryan Rakvic, Richard A. Hankins, Ed Grochowski, Hong Wang, Murali Annavaram, David K. Poulsen, Sanjiv Shah, John Shen, Gautham Chinya
  • Publication number: 20140115594
    Abstract: Method, apparatus and system embodiments to schedule OS-independent “shreds” without intervention of an operating system. For at least one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. A scheduler routine may run on each enabled sequencer. The schedulers may retrieve shred descriptors from a queue system. The sequencer associated with the scheduler may then execute the shred described by the descriptor. Other embodiments are also described and claimed.
    Type: Application
    Filed: October 30, 2013
    Publication date: April 24, 2014
    Inventors: Richard A. Hankins, Hong Wang, Gautham N. Chinya, Trung A. Diep, Shivnandan D. Kaushik, Bryant E. Bigbee, John P. Shen, Asit K. Mallick, Baiju V. Patel, James Paul Held, Milind B. Girkar, Prashant Sethi, Xinmin Tian
  • Patent number: 8689215
    Abstract: Methods, data structures, instructions, and techniques for structured exception handling for user-level threads in a multi-threading system are provided. Registered filter routines may be dispatched to a thread unit not managed by the operating system (OS). The dispatch may occur by allowing an OS-managed thread unit (proxy) to invoke the OS-provided structured exception handling service (including dispatcher) on behalf of the sequestered thread unit. Alternatively, an OS-managed thread unit may include dispatch code and may, without OS intervention, dispatch the filter routine to the sequestered thread unit. Other embodiments are also described and claimed.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: April 1, 2014
    Assignee: Intel Corporation
    Inventors: Richard A. Hankins, Gautham N. Chinya, Hong Wang, David K. Poulsen, Shirish Aundhe, Baiju V. Patel, Sanjiv M. Shah
  • Patent number: 8607235
    Abstract: Method, apparatus and system embodiments to schedule OS-independent “shreds” without intervention of an operating system. For at least one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. A scheduler routine may run on each enabled sequencer. The schedulers may retrieve shred descriptors from a queue system. The sequencer associated with the scheduler may then execute the shred described by the descriptor. Other embodiments are also described and claimed.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: December 10, 2013
    Assignee: Intel Corporation
    Inventors: Richard A. Hankins, Hong Wang, Gautham N. Chinya, Trung A. Diep, Shivnandan D. Kaushik, Bryant E. Bigbee, John P. Shen, Asit K. Mallick, Baiju V. Patel, James Paul Held, Milind B. Girkar, Prashant Sethi, Xinmin Tian
  • Publication number: 20130275735
    Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.
    Type: Application
    Filed: June 11, 2013
    Publication date: October 17, 2013
    Inventors: Gautham Chinya, Hong Wang, Prashant Sethi, Shivnandan Kaushik, Bryant Bigbee, John Shen, Richard Hankins, Xiang Zou, Baiju V. Patel, Jason W. Brandt, Anil Aggarwal, John L. Reid
  • Publication number: 20130219399
    Abstract: In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.
    Type: Application
    Filed: March 15, 2013
    Publication date: August 22, 2013
    Inventors: Hong Wang, John Shen, Edward Grochowski, Richard Hankins, Gautham Chinya, Bryant Bigbee, Shivnandan Kaushik, Xiang Chris Zou, Per Hammarlund, Scott Dion Rodgers, Xinmin Tian, Anil Aggawal, Prashant Sethi, Baiju Patel, James Held
  • Patent number: 8516483
    Abstract: Operating system services are transparently triggered for thread execution resources (“sequencers”) that are sequestered from view of the operating system. A “surrogate” thread that is managed by, and visible to, the operating system is utilized to acquire OS services on behalf of a sequestered sequencer. Multi-shred contention for shred-specific resources may thus be alleviated. Other embodiments are also described and claimed.
    Type: Grant
    Filed: May 13, 2005
    Date of Patent: August 20, 2013
    Assignee: Intel Corporation
    Inventors: Gautham Chinya, Hong Wang, Richard A. Hankins, Shivnandan D. Kaushik, Bryant Bigbee, John Shen, Prashant Sethi, Baiju V. Patel, John L. Reid
  • Publication number: 20130205122
    Abstract: In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.
    Type: Application
    Filed: March 8, 2013
    Publication date: August 8, 2013
    Inventors: Hong WANG, John SHEN, Hong JIANG, Richard HANKINS, Per HAMMARLUND, Dion RODGERS, Gautham CHINYA, Baiju PATEL, Shiv KAUSHIK, Bryant BIGBEE, Gad SHEAFFER, Yoav Talgam, Yuval YOSEF, James P. HELD
  • Patent number: 8479217
    Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: July 2, 2013
    Assignee: Intel Corporation
    Inventors: Gautham Chinya, Hong Wang, Prashant Sethi, Shivnandan Kaushik, Bryant Bigbee, John Shen, Richard Hankins, Xiang Zou, Baiju V. Patel, Jason W. Brandt, Anil Aggarwal, John L. Reid
  • Patent number: 8205200
    Abstract: Method, apparatus and system embodiments to schedule user-level OS-independent “shreds” without intervention of an operating system. For at least one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. The scheduler routine may receive compiler-generated hints from a compiler. The compiler hints may be generated by the compiler without user-provided pragmas, and may be passed to the scheduler routine via an API-like interface. The interface may include a scheduling hint data structure that is maintained by the compiler. Other embodiments are also described and claimed.
    Type: Grant
    Filed: November 29, 2005
    Date of Patent: June 19, 2012
    Assignee: Intel Corporation
    Inventors: Shih-wei Liao, Ryan N. Rakvic, Richard A. Hankins, Hong Wang, Gansha Wu, Guei-Yuan Lueh, Xinmin Tian, Paul M. Petersen, Sanjiv Shah, Trung Diep, John Shen, Gautham Chinya
  • Publication number: 20120131366
    Abstract: A first execution time of a first thread executing on a first processing unit of a multiprocessor is determined. A second execution time of a second thread executing on a second processing unit of the multiprocessor is determined, the first and second threads executing in parallel. Power is set to the first and second processing units to effectuate the first and second threads to finish executing at approximately the same time in future executions of the first and second threads. Other embodiments are also described and claimed.
    Type: Application
    Filed: January 20, 2012
    Publication date: May 24, 2012
    Inventors: Ryan Rakvic, Richard A. Hankins, Ed Grochowski, Hong Wang, Murali Annavaram, David K. Poulsen, Sanjiv Shah, John Shen, Gautham Chinya
  • Patent number: 8108863
    Abstract: A first execution time of a first thread executing on a first processing unit of a multiprocessor is determined. A second execution time of a second thread executing on a second processing unit of the multiprocessor is determined, the first and second threads executing in parallel. Power is set to the first and second processing units to effectuate the first and second threads to finish executing at approximately the same time in future executions of the first and second threads. Other embodiments are also described and claimed.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: January 31, 2012
    Assignee: Intel Corporation
    Inventors: Ryan Rakvic, Richard A. Hankins, Ed Grochowski, Hong Wang, Murali Annavaram, David K. Poulsen, Sanjiv Shah, John Shen, Gautham Chinya
  • Publication number: 20120017221
    Abstract: A technique to monitor software thread performance and update software that issues or uses the thread(s) to reduce performance-inhibiting events. At least one embodiment of the invention uses hardware and/or software timers or counters to monitor various events associated with executing user-level threads and report these events back to a user-level software program, which can use the information to avoid or at least reduce performance-inhibiting events associated with the user-level threads.
    Type: Application
    Filed: July 26, 2011
    Publication date: January 19, 2012
    Inventors: Richard A. Hankins, Gautham N. Chinya, Hong Wang, Shivnandan D. Kaushik, Bryant E. Bigbee, John P. Shen, Trung A. Diep, Xiang Zou, Baiju V. Patel, Paul M. Petersen, Sanjiv M. Shah, Ryan N. Rakvic, Prashant Sethi
  • Publication number: 20110314480
    Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.
    Type: Application
    Filed: August 30, 2011
    Publication date: December 22, 2011
    Inventors: Gautham Chinya, Hong Wang, Prashant Sethi, Shivnandan Kaushik, Bryant Bigbee, John Shen, Richard Hankins, Zou Xiang, Baiju V. Patel, Jason W. Brandt, Anil Aggarwal, John L. Reid
  • Patent number: 8079035
    Abstract: Data structure creation, organization and management techniques for data local to user-level threads are provided. In one embodiment, a method includes generating, for a user-level thread (“shred”) to run on a thread unit that is not managed by an operating system (“OS”), a storage area for local data and maintaining state in the storage area across a context switch from the thread unit that is not managed by the OS to a second thread unit that is managed by the OS. Other embodiments are also described and claimed.
    Type: Grant
    Filed: December 27, 2005
    Date of Patent: December 13, 2011
    Assignee: Intel Corporation
    Inventors: Richard A. Hankins, Gautham N. Chinya, Hong Wang, David K. Poulsen, Shirish Aundhe, John P. Shen, Sanjiv M. Shah, Baiju V. Patel
  • Patent number: 8074274
    Abstract: In one embodiment, the present invention includes a method for receiving a request from a user-level agent for programming of a user-level privilege for at least one architectural resource of an application-managed sequencer (AMS) and programming the user-level privilege for the at least one architectural resource using an operating system-managed sequencer (OMS) coupled to the AMS. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: December 6, 2011
    Assignee: Intel Corporation
    Inventors: Hong Wang, Gautham Chinya, Perry Wang, Jamison Collins, Richard A. Hankins, Per Hammarlund, John Shen
  • Patent number: 8028295
    Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: September 27, 2011
    Assignee: Intel Corporation
    Inventors: Gautham Chinya, Hong Wang, Prashant Sethi, Shivnandan Kaushik, Bryant Bigbee, John Shen, Richard Hankins, Xiang Zou, Baiju V. Patel, Jason W. Brandt, Anil Aggarwal, John L. Reid
  • Patent number: 8010969
    Abstract: A technique to monitor software thread performance and update software that issues or uses the thread(s) to reduce performance-inhibiting events. At least one embodiment of the invention uses hardware and/or software timers or counters to monitor various events associated with executing user-level threads and report these events back to a user-level software program, which can use the information to avoid or at least reduce performance-inhibiting events associated with the user-level threads.
    Type: Grant
    Filed: June 13, 2005
    Date of Patent: August 30, 2011
    Assignee: Intel Corporation
    Inventors: Richard A. Hankins, Gautham N. Chinya, Hong Wang, Shivnandan D. Kaushik, Bryant E. Bigbee, John P. Shen, Trung A. Diep, Xiang Zou, Baiju V. Patel, Paul M. Petersen, Sanjiv M. Shah, Ryan N. Rakvic, Prashant Sethi
  • Patent number: 7926330
    Abstract: An air/fuel imbalance detection module includes a fueling control module, a response time determination module, and a comparison module. The fueling control module commands a fueling change according to a predetermined fueling pattern. The response time determination module determines a measured response time for a wide-range air/fuel sensor (WRAF) to output a predetermined voltage. The comparison module compares the measured response time with a reference time range and diagnoses air/fuel imbalance when the measured response time is outside the reference time range.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: April 19, 2011
    Assignee: DENSO International America, Inc.
    Inventors: Zhe Huang, Richard Hankins