Patents by Inventor Richard Ho
Richard Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8771807Abstract: Described herein are organoaminosilane precursors which can be used to deposit silicon containing films which contain silicon and methods for making these precursors. Also disclosed herein are deposition methods for making silicon-containing films or silicon containing films using the organoaminosilane precursors described herein. Also disclosed herein are the vessels that comprise the organoaminosilane precursors or a composition thereof that can be used, for example, to deliver the precursor to a reactor in order to deposit a silicon-containing film.Type: GrantFiled: May 17, 2012Date of Patent: July 8, 2014Assignee: Air Products and Chemicals, Inc.Inventors: Manchao Xiao, Xinjian Lei, Bing Han, Mark Leonard O'Neill, Ronald Martin Pearlstein, Richard Ho, Haripin Chandra, Agnes Derecskei-Kovacs
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Publication number: 20140158580Abstract: Described herein are alkoxysilylamine precursors having the following Formulae A and B: wherein R1 and R4 are independently selected from a linear or branched C1 to C10 alkyl group, a C3 to C12 alkenyl group, a C3 to C12 alkynyl group, a C4 to C10 cyclic alkyl group, and a C6 to C10 aryl group and wherein R2, R3, R4, R5, and R6 are independently selected from the group consisting of hydrogen, a linear or branched C1 to C10 alkyl group, a C2 to C12 alkenyl group, a C2 to C12 alkynyl group, a C4 to C10 cyclic alkyl, a C6 to C10 aryl group, and a linear or branched C1 to C10 alkoxy group. Also described herein are deposition processes using at least one precursor have Formulae A and/or B described herein.Type: ApplicationFiled: December 4, 2013Publication date: June 12, 2014Applicant: AIR PRODUCTS AND CHEMICALS, INC.Inventors: Manchao Xiao, Ronald Martin Pearlstein, Richard Ho, Daniel P. Spence, Xinjian Lei
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Publication number: 20130243968Abstract: A formulation comprising a first organosilane precursor and a halogenation reagent wherein at least a portion or all of the halogenation reagent reacts to provide the second organosilane precursor. Methods of generating such formulation in situ from readily available pure materials are also provided. Further provided are methods of using the formulations as the precursor for a flowable vapor deposition process.Type: ApplicationFiled: March 12, 2013Publication date: September 19, 2013Applicant: AIR PRODUCTS AND CHEMICALS, INC.Inventors: Manchao Xiao, Ronald Martin Pearlstein, Agnes Derecskei-Kovacs, Xinjian Lei, Richard Ho, Mark Leonard O'Neill, Daniel P. Spence, Steven Gerard Mayorga
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Publication number: 20130239084Abstract: The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false answer cannot be provided e.g. when stopped due to resource constraints. In some embodiments, a measure of value N indicates that a given property that is being checked will not be violated within a distance N from an initial state from which the analysis started. Therefore, in such embodiments, a measure of value N indicates that the analysis has implicitly or explicitly covered every possible excursion of length N from the initial state, and formally proved that no counter-example is possible within this length N.Type: ApplicationFiled: April 8, 2013Publication date: September 12, 2013Applicant: Mentor Graphics CorporationInventors: Jeremy Rutledge Levitt, Christophe Gauthron, Chian-Min Richard Ho, Ping Fai Yeung, Kalyana C. Mulam, Ramesh Sathianathan
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Publication number: 20130129940Abstract: Described herein are organoaminosilane precursors which can be used to deposit silicon containing films which contain silicon and methods for making these precursors. Also disclosed herein are deposition methods for making silicon-containing films or silicon containing films using the organoaminosilane precursors described herein. Also disclosed herein are the vessels that comprise the organoaminosilane precursors or a composition thereof that can be used, for example, to deliver the precursor to a reactor in order to deposit a silicon-containing film.Type: ApplicationFiled: May 17, 2012Publication date: May 23, 2013Applicant: AIR PRODUCTS AND CHEMICALS, INC.Inventors: Manchao Xiao, Xinjian Lei, Bing Han, Mark Leonard O'Neill, Ronald Martin Pearlstein, Richard Ho, Haripin Chandra, Agnes Derecskei-Kovacs
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Patent number: 8418121Abstract: The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false answer cannot be provided e.g. when stopped due to resource constraints. In some embodiments, a measure of value N indicates that a given property that is being checked will not be violated within a distance N from an initial state from which the analysis started. Therefore, in such embodiments, a measure of value N indicates that the analysis has implicitly or explicitly covered every possible excursion of length N from the initial state, and formally proved that no counter-example is possible within this length N.Type: GrantFiled: February 14, 2011Date of Patent: April 9, 2013Assignee: Mentor Graphics CorporationInventors: Jeremy Rutledge Levitt, Christophe Gauthron, Chian-Min Richard Ho, Ping Fai Yeung, Kalyana C. Mulam, Ramesh Sathianathan
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Publication number: 20110138346Abstract: The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false answer cannot be provided e.g. when stopped due to resource constraints. In some embodiments, a measure of value N indicates that a given property that is being checked will not be violated within a distance N from an initial state from which the analysis started. Therefore, in such embodiments, a measure of value N indicates that the analysis has implicitly or explicitly covered every possible excursion of length N from the initial state, and formally proved that no counter-example is possible within this length N.Type: ApplicationFiled: February 14, 2011Publication date: June 9, 2011Applicant: Mentor Graphics CorporationInventors: Jeremy Rutledge Levitt, Christophe Gauthron, Chian-Min Richard Ho, Ping Fai Yeung, Kalyana C. Mulam, Ramesh Sathianathan
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Patent number: 7890897Abstract: The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false answer cannot be provided e.g. when stopped due to resource constraints. In some embodiments, a measure of value N indicates that a given property that is being checked will not be violated within a distance N from an initial state from which the analysis started. Therefore, in such embodiments, a measure of value N indicates that the analysis has implicitly or explicitly covered every possible excursion of length N from the initial state, and formally proved that no counter-example is possible within this length N.Type: GrantFiled: November 13, 2007Date of Patent: February 15, 2011Assignee: Mentor Graphics CorporationInventors: Jeremy Rutledge Levitt, Christophe Gauthron, Chian-Min Richard Ho, Ping Fai Yeung, Kalyana C. Mulam, Ramesh Sathianathan
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Patent number: 7478028Abstract: A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first-controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.Type: GrantFiled: January 12, 2005Date of Patent: January 13, 2009Inventors: Chian-Min Richard Ho, Robert Kristianto Mardjuki, David Lansing Dill, Jing Chyuarn Lin, Ping Fai Yeung, Paul II Estrada, Jean-Charles Giomi, Tai An Ly, Kalyana C. Mulam, Lawrence Curtis Widdoes, Jr., Paul Andrew Wilcox
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Patent number: 7454324Abstract: A computer is programmed to automatically select a state or a set of states of a digital circuit that are visited during simulation, for use as one or more initial states by a formal verification tool. Such automatic selection of one or more simulation states reduces the set of all simulation states to a small subset, thereby to address the state space explosion problem. Depending on the embodiment, the programmed computer uses one or more criteria provided by a library and/or by the user, in making its selection of states. Such criteria may be based on a property (assertion/checker) of the digital circuit and/or a signal generated during simulation. Furthermore, after such criteria (also called “primary criteria”) are applied, the selected states may be pruned by application of additional criteria (also called “secondary criteria”) prior to formal analysis.Type: GrantFiled: January 10, 2003Date of Patent: November 18, 2008Inventors: James Andrew Garrard Seawright, Ramesh Sathianathan, Christophe G. Gauthron, Jeremy R. Levitt, Kalyana C. Mulam, Chian-Min Richard Ho, Ping Fai Yeung
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Patent number: 7318205Abstract: The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false answer cannot be provided e.g. when stopped due to resource constraints. In some embodiments, a measure of value N indicates that a given property that is being checked will not be violated within a distance N from an initial state from which the analysis started. Therefore, in such embodiments, a measure of value N indicates that the analysis has implicitly or explicitly covered every possible excursion of length N from the initial state, and formally proved that no counter-example is possible within this length N.Type: GrantFiled: December 6, 2004Date of Patent: January 8, 2008Inventors: Jeremy Rutledge Levitt, Christophe Gauthron, Chian-Min Richard Ho, Ping Fai Yeung, Kalyana C. Mulam, Ramesh Sathianathan
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Patent number: 7007249Abstract: A programmed computer generates descriptions of circuits (called “checkers”) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die. The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging defective behavior.Type: GrantFiled: January 20, 2003Date of Patent: February 28, 2006Inventors: Tai An Ly, Jean-Charles Giomi, Kalyana C. Mulam, Paul Andrew Wilcox, David Lansing Dill, Paul II Estrada, Chian-Min Richard Ho, Jing Chyuarn Lin, Robert Kristianto Mardjuki, Lawrence Curtis Widdoes, Jr., Ping Fai Yeung
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Patent number: 6885983Abstract: A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.Type: GrantFiled: May 4, 2001Date of Patent: April 26, 2005Assignee: Mentor Graphics CorporationInventors: Chian-Min Richard Ho, Robert Kristianto Mardjuki, David Lansing Dill, Jing Chyuarn Lin, Ping Fai Yeung, Paul Il Estrada, Jean-Charles Giomi, Tai An Ly, Kalyana C. Mulam, Lawrence Curtis Widdoes, Jr., Paul Andrew Wilcox
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Publication number: 20050084531Abstract: A tablet core containing a water-soluble, preferably highly water-soluble, active ingredient is coated for sustained release with an aqueous-based coating of an ethyl acrylate-methyl methacrylate copolymer. The amount of copolymer applied, on a dry basis, being about 0.5% to about 2% by weight, based on the total weight of the coated tablet. The coated tablet is dried for not more than about 30 minutes, preferably for about 10 to about 15 minutes, at about 50° C. Notwithstanding the greatly shortened drying time and/or low percentage of copolymner applied, the coated tablet surprisingly exhibits a substantially stable dissolution profile. Tablets containing potassium chloride and coated in accordance with the invention surprisingly exhibit a dissolution profile comparable to that afforded by potassium chloride tablets coated for sustained release with an organic solvent-based coating.Type: ApplicationFiled: October 14, 2004Publication date: April 21, 2005Inventors: Jatin Desai, Roger Stanko, Ronald Miller, Richard Ho
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Patent number: 6848088Abstract: The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false answer cannot be provided e.g. when stopped due to resource constraints. In some embodiments, a measure of value N indicates that a given property that is being checked will not be violated within a distance N from an initial state from which the analysis started. Therefore, in such embodiments, a measure of value N indicated that the analysis has implicitly or explicitly covered every possible excursion of length N from the initial state, and formally proved that no counter-example is possible within this length N.Type: GrantFiled: June 17, 2002Date of Patent: January 25, 2005Assignee: Mentor Graphics CorporationInventors: Jeremy Rutledge Levitt, Christophe Gauthron, Chian-Min Richard Ho, Ping Fai Yeung, Kalyana C. Mulam, Ramesh Sathianathan
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Publication number: 20040107132Abstract: A computer-implemented decision management system which provides qualitative client assessment via point in time simulation. More specifically, the decision management system (a) simulates the effect of a strategy by applying the strategy to client data, and (b) tracks what type of client traveled through a respective decision point in the strategy during the simulation. Simulation parameters can be selected without technical intervention via, for example, a GUI and a relational data model. Such parameters can include which customers and which client data sample will be used for the simulation, and which inbound events will trigger the strategy. Moreover, detailed and aggregate results can be consolidated to determine expected results from the simulated strategies, and traditional and OLAP reporting facilities can be applied to analyze/view the consolidated results.Type: ApplicationFiled: November 24, 2003Publication date: June 3, 2004Applicant: American Management Systems, Inc.Inventors: Laurence Honarvar, Richard Ho, Len Burt
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Patent number: 6684192Abstract: A computer-implemented decision management system which provides qualitative client assessment via point in time simulation. More specifically, the decision management system (a) simulates the effect of a strategy by applying the strategy to client data, and (b) tracks what type of client traveled through a respective decision point in the strategy during the simulation. Simulation parameters can be selected without technical intervention via, for example, a GUI and a relational data model. Such parameters can include which customers and which client data sample will be used for the simulation, and which inbound events will trigger the strategy. Moreover, detailed and aggregate results can be consolidated to determine expected results from the simulated strategies, and traditional and OLAP reporting facilities can be applied to analyze/view the consolidated results.Type: GrantFiled: April 23, 2002Date of Patent: January 27, 2004Assignee: American Management Systems, Inc.Inventors: Laurence Honarvar, Richard Ho, Len Burt
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Publication number: 20030200515Abstract: A programmed computer generates descriptions of circuits (called “checkers”) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die. The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging defective behavior.Type: ApplicationFiled: January 20, 2003Publication date: October 23, 2003Applicant: 0-In Design automation Inc.Inventors: Tai An Ly, Jean-Charles Giomi, Kalyana C. Mulam, Paul Andrew Wilcox, David Lansing Dill, Paul Ii Estrada, Chian-Min Richard Ho, Jing Chyuarn Lin, Robert Kristianto Mardjuki, Lawrence Curtis Widdoes, Ping Fai Yeung
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Patent number: 6609229Abstract: A programmed computer generates descriptions of circuits (called “checkers”) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging detective behavior.Type: GrantFiled: August 9, 2000Date of Patent: August 19, 2003Assignee: O-In Design Automation, Inc.Inventors: Tai An Ly, Jean-Charles Giomi, Kalyana C. Mulam, Paul Andrew Wilcox, David Lansing Dill, Paul Estrada, II, Chian-Min Richard Ho, Jing Chyuarn Lin, Robert Kristianto Mardjuki, Lawrence Curtis Widdoes, Jr., Ping Fai Yeung
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Patent number: D476541Type: GrantFiled: September 24, 2001Date of Patent: July 1, 2003Inventors: Robert G. Kushner, Richard Ho