Abstract: A frequency synthesizer of the pulse cancellation type which predicts the phase jitter that will be caused by the pulse cancellation and generates a compensation signal C which precisely compensates for the phase jitter. The compensation signal is derived directly, from a pulse train in the synthesizer which itself contains jitter, via a d.c. removal circuit DCR and an analogue integrator INT.

Abstract: A frequency synthesizer of the type which selects pulses from a clock pulse generator (21) to provide a lower output frequency Fo, the synthesizer including an accumulator (22) of the type which, for each input pulse thereto, adds a preselected increment Y to the accumulated value in the accumulator and gives an overflow pulse each time an accumulated value C (where C is equal to or greater than Y) is reached or exceeded and leaves any excess (residue) in the accumulator. In accordance with the invention, adjustable delay means are coupled to the accumulator output such that each output pulse is delayed by an amount which depends on the residue in the accumulator thereby providing a spectrally pure output frequency.